From: Ajit Khaparde <ajitkhaparde@gmail.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Subject: [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip
Date: Mon, 11 Jan 2021 09:43:58 -0800
Message-ID: <20210111174400.10606-5-ajit.khaparde@broadcom.com> (raw)
In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com>
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support
TPA on the new chip.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------
drivers/net/bnxt/bnxt_rxr.h | 12 ++++++-
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 14901f1b9..af3f9b936 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
return mbuf;
}
+static void bnxt_tpa_get_metadata(struct bnxt *bp,
+ struct bnxt_tpa_info *tpa_info,
+ struct rx_tpa_start_cmpl *tpa_start,
+ struct rx_tpa_start_cmpl_hi *tpa_start1)
+{
+ tpa_info->cfa_code_valid = 0;
+ tpa_info->vlan_valid = 0;
+ tpa_info->hash_valid = 0;
+ tpa_info->l4_csum_valid = 0;
+
+ if (likely(tpa_start->flags_type &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
+ tpa_info->hash_valid = 1;
+ tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
+ }
+
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
+ struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
+ (void *)tpa_start1;
+
+ if (v2_tpa_start->agg_id &
+ RX_TPA_START_V2_CMPL_METADATA1_VALID) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan =
+ rte_le_to_cpu_16(v2_tpa_start1->metadata0);
+ }
+
+ if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ tpa_info->l4_csum_valid = 1;
+
+ return;
+ }
+
+ tpa_info->cfa_code_valid = 1;
+ tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ if (tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
+ }
+
+ if (likely(tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+ tpa_info->l4_csum_valid = 1;
+}
+
static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
struct rx_tpa_start_cmpl *tpa_start,
struct rx_tpa_start_cmpl_hi *tpa_start1)
@@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
mbuf->ol_flags = PKT_RX_LRO;
- if (likely(tpa_start->flags_type &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
- mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
+
+ bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
+
+ if (likely(tpa_info->hash_valid)) {
+ mbuf->hash.rss = tpa_info->rss_hash;
mbuf->ol_flags |= PKT_RX_RSS_HASH;
- } else {
- mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ } else if (tpa_info->cfa_code_valid) {
+ mbuf->hash.fdir.id = tpa_info->cfa_code;
mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
}
- if (tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
- mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
+
+ if (tpa_info->vlan_valid) {
+ mbuf->vlan_tci = tpa_info->vlan;
mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
}
- if (likely(tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+
+ if (likely(tpa_info->l4_csum_valid))
mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
/* recycle next mbuf */
@@ -751,7 +800,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
+ if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
+ cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
(struct rx_tpa_start_cmpl_hi *)rxcmp1);
rc = -EINVAL; /* Continue w/o new mbuf */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index b2942030a..78814edbb 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -50,6 +50,14 @@ struct bnxt_tpa_info {
uint16_t len;
uint32_t agg_count;
struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
+
+ uint32_t rss_hash;
+ uint32_t vlan;
+ uint16_t cfa_code;
+ uint8_t hash_valid:1;
+ uint8_t vlan_valid:1;
+ uint8_t cfa_code_valid:1;
+ uint8_t l4_csum_valid:1;
};
struct bnxt_rx_ring_info {
@@ -122,4 +130,6 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
-#endif
+
+#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
next prev parent reply other threads:[~2021-01-11 17:44 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-20 5:24 [dpdk-dev] [PATCH 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2020-12-20 5:24 ` [dpdk-dev] [PATCH 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-11 17:43 ` Ajit Khaparde [this message]
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
2021-01-11 17:44 ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-12 3:39 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
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