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From: Ajit Khaparde <ajitkhaparde@gmail.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Subject: [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation
Date: Mon, 11 Jan 2021 09:43:59 -0800
Message-ID: <20210111174400.10606-6-ajit.khaparde@broadcom.com> (raw)
In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com>

From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>

Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.

In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.

Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c | 60 ++++++++++++++++++++--------------
 drivers/net/bnxt/bnxt_hwrm.c   |  3 ++
 2 files changed, 39 insertions(+), 24 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 8ca4fb151..e11751cc1 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4212,39 +4212,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
 
 	ctx_pg = &ctx->qp_mem;
 	ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
-	mem_size = ctx->qp_entry_size * ctx_pg->entries;
-	rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
-	if (rc)
-		return rc;
+	if (ctx->qp_entry_size) {
+		mem_size = ctx->qp_entry_size * ctx_pg->entries;
+		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
+		if (rc)
+			return rc;
+	}
 
 	ctx_pg = &ctx->srq_mem;
 	ctx_pg->entries = ctx->srq_max_l2_entries;
-	mem_size = ctx->srq_entry_size * ctx_pg->entries;
-	rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
-	if (rc)
-		return rc;
+	if (ctx->srq_entry_size) {
+		mem_size = ctx->srq_entry_size * ctx_pg->entries;
+		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
+		if (rc)
+			return rc;
+	}
 
 	ctx_pg = &ctx->cq_mem;
 	ctx_pg->entries = ctx->cq_max_l2_entries;
-	mem_size = ctx->cq_entry_size * ctx_pg->entries;
-	rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
-	if (rc)
-		return rc;
+	if (ctx->cq_entry_size) {
+		mem_size = ctx->cq_entry_size * ctx_pg->entries;
+		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
+		if (rc)
+			return rc;
+	}
 
 	ctx_pg = &ctx->vnic_mem;
 	ctx_pg->entries = ctx->vnic_max_vnic_entries +
 		ctx->vnic_max_ring_table_entries;
-	mem_size = ctx->vnic_entry_size * ctx_pg->entries;
-	rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
-	if (rc)
-		return rc;
+	if (ctx->vnic_entry_size) {
+		mem_size = ctx->vnic_entry_size * ctx_pg->entries;
+		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
+		if (rc)
+			return rc;
+	}
 
 	ctx_pg = &ctx->stat_mem;
 	ctx_pg->entries = ctx->stat_max_entries;
-	mem_size = ctx->stat_entry_size * ctx_pg->entries;
-	rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
-	if (rc)
-		return rc;
+	if (ctx->stat_entry_size) {
+		mem_size = ctx->stat_entry_size * ctx_pg->entries;
+		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
+		if (rc)
+			return rc;
+	}
 
 	min = ctx->tqm_min_entries_per_ring;
 
@@ -4260,10 +4270,12 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
 	for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
 		ctx_pg = ctx->tqm_mem[i];
 		ctx_pg->entries = i ? entries : entries_sp;
-		mem_size = ctx->tqm_entry_size * ctx_pg->entries;
-		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
-		if (rc)
-			return rc;
+		if (ctx->tqm_entry_size) {
+			mem_size = ctx->tqm_entry_size * ctx_pg->entries;
+			rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
+			if (rc)
+				return rc;
+		}
 		ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
 	}
 
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 56e2e33a9..6d54b1656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -64,6 +64,9 @@ static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
 				  uint8_t *pg_attr,
 				  uint64_t *pg_dir)
 {
+	if (rmem->nr_pages == 0)
+		return;
+
 	if (rmem->nr_pages > 1) {
 		*pg_attr = 1;
 		*pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
-- 
2.21.1 (Apple Git-122.3)


  parent reply	other threads:[~2021-01-11 17:44 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-20  5:24 [dpdk-dev] [PATCH 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-03  3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-08  5:12   ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-08  5:13     ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
2021-01-08  5:13     ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-11 17:43     ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-11 17:43       ` Ajit Khaparde [this message]
2021-01-11 17:44       ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-12  3:39       ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde

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