From: kumar amber <kumar.amber@intel.com>
To: dev@dpdk.org
Cc: bruce.richardson@intel.com
Subject: [dpdk-dev] [PATCH v1] lib/hash: support non sse42 cpu architecture
Date: Tue, 12 Jan 2021 12:54:46 +0530 [thread overview]
Message-ID: <20210112072446.880122-1-kumar.amber@intel.com> (raw)
add _SSE42_ flag to enable compilation of
sse42 specific instructions only on supported
architecture
Signed-off-by: kumar amber <kumar.amber@intel.com>
---
lib/librte_hash/rte_hash_crc.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index 3e131aa6bb..e9f063780c 100644
--- a/lib/librte_hash/rte_hash_crc.h
+++ b/lib/librte_hash/rte_hash_crc.h
@@ -358,7 +358,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
return crc;
}
-#if defined(RTE_ARCH_X86)
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
static inline uint32_t
crc32c_sse42_u8(uint8_t data, uint32_t init_val)
{
@@ -404,7 +404,7 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
}
#endif
-#ifdef RTE_ARCH_X86_64
+#if defined(RTE_ARCH_X86_64) && defined(__SSE42__)
static inline uint32_t
crc32c_sse42_u64(uint64_t data, uint64_t init_val)
{
@@ -442,7 +442,7 @@ static uint8_t crc32_alg = CRC32_SW;
static inline void
rte_hash_crc_set_alg(uint8_t alg)
{
-#if defined(RTE_ARCH_X86)
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (alg == CRC32_SSE42_x64 &&
!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
alg = CRC32_SSE42;
@@ -471,7 +471,7 @@ RTE_INIT(rte_hash_crc_init_alg)
static inline uint32_t
rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_X86
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u8(data, init_val);
#endif
@@ -494,7 +494,7 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_X86
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u16(data, init_val);
#endif
@@ -517,7 +517,7 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_X86
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u32(data, init_val);
#endif
@@ -540,12 +540,12 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
{
-#ifdef RTE_ARCH_X86_64
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (likely(crc32_alg == CRC32_SSE42_x64))
return crc32c_sse42_u64(data, init_val);
#endif
-#if defined RTE_ARCH_X86
+#if defined(RTE_ARCH_X86) && defined(__SSE42__)
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u64_mimic(data, init_val);
#endif
--
2.25.1
next reply other threads:[~2021-01-12 7:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 7:24 kumar amber [this message]
2021-03-24 21:20 ` Thomas Monjalon
2021-03-24 22:59 ` Wang, Yipeng1
2021-03-25 8:06 ` Thomas Monjalon
2021-04-08 22:41 ` Thomas Monjalon
2021-04-08 23:01 ` Stephen Hemminger
2021-04-09 3:17 ` Amber, Kumar
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