From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 623A4A0A03; Mon, 18 Jan 2021 10:37:09 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC84D140D19; Mon, 18 Jan 2021 10:37:08 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD8FF140D0A for ; Mon, 18 Jan 2021 10:37:07 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10I9QqGZ001601 for ; Mon, 18 Jan 2021 01:37:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=ibenRgilcfo0nvX0eaJ5yETvDwWkld9VrjSdWo1xTl8=; b=cvIA1t5Uxfpl8XHFzWfv3PDPAitcYLACNmZOcVgOpkquCg14s7+gs2gacnudi112RSn1 JfcUD8y/vtmk15Kn91u3iBJ0T8DJBlfLwSnhZMvUJbtj7ga460hBpd9gI/WEt4OTzy6d fs0ar5+fvVjMKghhj533hpNfim868+RnBq5oetfVTvW9NLkYHXk4GVYiiIgpxCxwIqR7 BNmePEvIcA/yVywlRM8eQ9575e0cC4jul+Sc8OGtlZm0UcXmOlidvnYy7u8K91VFfCXd UT0aUBb4nFK6FpujSn75jh7hvBg+cV1b4zBOScGBBDe65XyIss3WtYoI1Zpf2+PSTw7N xg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3640hsu1xj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 18 Jan 2021 01:37:06 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Jan 2021 01:37:04 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Jan 2021 01:37:04 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Jan 2021 01:37:04 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 21A853F703F; Mon, 18 Jan 2021 01:37:04 -0800 (PST) From: Nalla Pradeep To: Jerin Jacob , Nithin Dabilpuram , Nalla Pradeep , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: , Date: Mon, 18 Jan 2021 09:35:53 +0000 Message-ID: <20210118093602.5449-2-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118093602.5449-1-pnalla@marvell.com> References: <20210118093602.5449-1-pnalla@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-18_07:2021-01-15, 2021-01-18 signatures=0 Subject: [dpdk-dev] [PATCH v2 02/11] net/octeontx_ep: add ethdev probe and remove X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" add basic PCIe ethdev probe and remove. Signed-off-by: Nalla Pradeep --- drivers/common/octeontx2/otx2_common.h | 5 +- drivers/net/octeontx_ep/meson.build | 13 +++++ drivers/net/octeontx_ep/otx_ep_common.h | 14 +++++ drivers/net/octeontx_ep/otx_ep_ethdev.c | 62 +++++++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_vf.h | 9 ++++ drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 6 +-- 6 files changed, 105 insertions(+), 4 deletions(-) create mode 100644 drivers/net/octeontx_ep/otx_ep_common.h create mode 100644 drivers/net/octeontx_ep/otx_ep_vf.h diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h index b6779f7104..cd52e098e6 100644 --- a/drivers/common/octeontx2/otx2_common.h +++ b/drivers/common/octeontx2/otx2_common.h @@ -136,7 +136,10 @@ extern int otx2_logtype_ree; #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081 -#define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */ +#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */ +/* OCTEON TX2 98xx EP mode */ +#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103 +#define PCI_DEVID_OCTEONTX2_EP_RAW_VF 0xB204 /* OCTEON TX2 EP mode */ #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF 0xA0f6 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF 0xA0f7 #define PCI_DEVID_OCTEONTX2_RVU_REE_PF 0xA0f4 diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build index 83ffbad7b6..06663de4e2 100644 --- a/drivers/net/octeontx_ep/meson.build +++ b/drivers/net/octeontx_ep/meson.build @@ -6,3 +6,16 @@ sources = files( 'otx_ep_ethdev.c', ) +extra_flags = [] +# This integrated controller runs only on a arm64 machine, remove 32bit warnings +if not dpdk_conf.get('RTE_ARCH_64') + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] +endif + +foreach flag: extra_flags + if cc.has_argument(flag) + cflags += flag + endif +endforeach + +includes += include_directories('../../common/octeontx2') diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h new file mode 100644 index 0000000000..3fa2de9ab3 --- /dev/null +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2020 Marvell. + */ +#ifndef _OTX_EP_COMMON_H_ +#define _OTX_EP_COMMON_H_ + +/* OTX_EP EP VF device data structure */ +struct otx_ep_device { + /* PCI device pointer */ + struct rte_pci_device *pdev; + + struct rte_eth_dev *eth_dev; +}; +#endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 2b2d684a0b..4eb75a2765 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -1,3 +1,65 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2020 Marvell. */ + +#include +#include +#include + +#include "otx2_common.h" +#include "otx_ep_common.h" +#include "otx_ep_vf.h" + +static int +otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) +{ + RTE_SET_USED(eth_dev); + + return -ENODEV; +} + +static int +otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) +{ + RTE_SET_USED(eth_dev); + + return -ENODEV; +} + +static int +otx_ep_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct otx_ep_device), + otx_ep_eth_dev_init); +} + +static int +otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, + otx_ep_eth_dev_uninit); +} + + +/* Set of PCI devices this driver supports */ +static const struct rte_pci_id pci_id_otx_ep_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) }, + { .vendor_id = 0, /* sentinel */ } +}; + + + +static struct rte_pci_driver rte_otx_ep_pmd = { + .id_table = pci_id_otx_ep_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = otx_ep_eth_dev_pci_probe, + .remove = otx_ep_eth_dev_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map); +RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci"); diff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h new file mode 100644 index 0000000000..0498dd0cf5 --- /dev/null +++ b/drivers/net/octeontx_ep/otx_ep_vf.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2020 Marvell. + */ +#ifndef _OTX_EP_VF_H_ +#define _OTX_EP_VF_H_ + +#define PCI_DEVID_OCTEONTX_EP_VF 0xa303 + +#endif /*_OTX_EP_VF_H_ */ diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c index 2b78a7941d..b2ccdda83e 100644 --- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c +++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c @@ -22,7 +22,7 @@ static const struct rte_pci_id pci_sdp_vf_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, - PCI_DEVID_OCTEONTX2_EP_VF) + PCI_DEVID_OCTEONTX2_EP_RAW_VF) }, { .vendor_id = 0, @@ -109,8 +109,8 @@ sdp_chip_specific_setup(struct sdp_device *sdpvf) int ret; switch (dev_id) { - case PCI_DEVID_OCTEONTX2_EP_VF: - sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_VF; + case PCI_DEVID_OCTEONTX2_EP_RAW_VF: + sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF; ret = sdp_vf_setup_device(sdpvf); break; -- 2.17.1