From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 913D7A0A03; Mon, 18 Jan 2021 10:37:26 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BBAA140D34; Mon, 18 Jan 2021 10:37:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 68B0A140D0A for ; Mon, 18 Jan 2021 10:37:08 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10I9QqGb001601; Mon, 18 Jan 2021 01:37:07 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=ArEq+trxBE4KVZDUUTwGlYABH/E2uRwvNVt7Nj4oRQY=; b=CluNkv+hjqhIA83Wa1lkxDK8R9v6397NHzIOZeJC66RN8nRWQy8II3GMIqJWJjRldj5I etij7EFLU1PHaRTsiSChkWxNS9/tx90a7Lw2SMqvJ0nRZ3lsUH62VxJ6p9uDhSzFFlQx RIiT2HYvg8aK2uATJlUFi2qsaKUGyzUbTe/MQR+gMfhRBAPb1iC+qy+Ndwrg2j6DKd/W waXUDYxu+4bO24gu7ZjufnxqlvLgzHtkHBL/0TWF3YrKGUUhHFCu6IkllGN4VaOGw/SA HBbFfDX6hUi/CWTBkcknOUR438TWKC9C+enDq4CvlxcgNLk1Q7yd5G7OSv7Sztyt8WnD JA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3640hsu1xj-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 18 Jan 2021 01:37:07 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Jan 2021 01:37:05 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Jan 2021 01:37:04 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Jan 2021 01:37:04 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 6D7423F7041; Mon, 18 Jan 2021 01:37:04 -0800 (PST) From: Nalla Pradeep To: Nalla Pradeep , Radha Mohan Chintakuntla , Veerasenareddy Burru , "Anatoly Burakov" CC: , , Date: Mon, 18 Jan 2021 09:35:54 +0000 Message-ID: <20210118093602.5449-3-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118093602.5449-1-pnalla@marvell.com> References: <20210118093602.5449-1-pnalla@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-18_07:2021-01-15, 2021-01-18 signatures=0 Subject: [dpdk-dev] [PATCH v2 03/11] net/octeontx_ep: add device init and uninit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add basic init and uninit function which includes initializing fields of ethdev private structure. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx_ep_common.h | 19 +++++- drivers/net/octeontx_ep/otx_ep_ethdev.c | 88 +++++++++++++++++++++++-- 2 files changed, 101 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 3fa2de9ab3..1c31ea8de2 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -4,11 +4,28 @@ #ifndef _OTX_EP_COMMON_H_ #define _OTX_EP_COMMON_H_ +#define otx_ep_printf(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \ + fmt, ##args) + +#define otx_ep_info(fmt, args...) \ + otx_ep_printf(INFO, fmt, ##args) + +#define otx_ep_err(fmt, args...) \ + otx_ep_printf(ERR, fmt, ##args) + +#define otx_ep_dbg(fmt, args...) \ + otx_ep_printf(DEBUG, fmt, ##args) + /* OTX_EP EP VF device data structure */ struct otx_ep_device { /* PCI device pointer */ struct rte_pci_device *pdev; - + uint16_t chip_id; struct rte_eth_dev *eth_dev; + int port_id; + /* Memory mapped h/w address */ + uint8_t *hw_addr; + int port_configured; }; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 4eb75a2765..a1afdfab67 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -10,20 +10,99 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" +#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) +static int +otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) +{ + struct rte_pci_device *pdev = otx_epvf->pdev; + uint32_t dev_id = pdev->id.device_id; + int ret; + + switch (dev_id) { + case PCI_DEVID_OCTEONTX_EP_VF: + otx_epvf->chip_id = dev_id; + break; + case PCI_DEVID_OCTEONTX2_EP_NET_VF: + case PCI_DEVID_CN98XX_EP_NET_VF: + otx_epvf->chip_id = dev_id; + break; + default: + otx_ep_err("Unsupported device\n"); + ret = -EINVAL; + } + + if (!ret) + otx_ep_info("OTX_EP dev_id[%d]\n", dev_id); + + return ret; +} + +/* OTX_EP VF device initialization */ +static int +otx_epdev_init(struct otx_ep_device *otx_epvf) +{ + if (otx_ep_chip_specific_setup(otx_epvf)) { + otx_ep_err("Chip specific setup failed\n"); + goto setup_fail; + } + + return 0; + +setup_fail: + return -ENOMEM; +} + static int otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + otx_epvf->port_configured = 0; + + if (eth_dev->data->mac_addrs != NULL) + rte_free(eth_dev->data->mac_addrs); - return -ENODEV; + return 0; } static int otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN]; - return -ENODEV; + /* Single process support */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pdev); + + if (pdev->mem_resource[0].addr) { + otx_ep_info("OTX_EP BAR0 is mapped:\n"); + } else { + otx_ep_err("OTX_EP: Failed to map device BARs\n"); + otx_ep_err("BAR0 %p\n", pdev->mem_resource[0].addr); + return -ENODEV; + } + otx_epvf->eth_dev = eth_dev; + otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) { + otx_ep_err("MAC addresses memory allocation failed\n"); + return -ENOMEM; + } + rte_eth_random_addr(vf_mac_addr); + memcpy(eth_dev->data->mac_addrs, vf_mac_addr, RTE_ETHER_ADDR_LEN); + otx_epvf->hw_addr = pdev->mem_resource[0].addr; + otx_epvf->pdev = pdev; + + otx_epdev_init(otx_epvf); + otx_epvf->port_configured = 0; + + return 0; } static int @@ -42,7 +121,6 @@ otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev) otx_ep_eth_dev_uninit); } - /* Set of PCI devices this driver supports */ static const struct rte_pci_id pci_id_otx_ep_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) }, -- 2.17.1