From: Nalla Pradeep <pnalla@marvell.com>
Cc: <jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>,
Nalla Pradeep <pnalla@marvell.com>
Subject: [dpdk-dev] [PATCH v3 09/11] net/octeontx_ep: Added dev start and stop
Date: Tue, 26 Jan 2021 13:30:49 -0800 [thread overview]
Message-ID: <20210126213051.57281-9-pnalla@marvell.com> (raw)
In-Reply-To: <20210126213051.57281-1-pnalla@marvell.com>
Dev start and stop operations are added. To accomplish this internal
functions to enable or disable io queues are incorporated.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/otx2_ep_vf.c | 107 ++++++++++++++++++++
drivers/net/octeontx_ep/otx_ep_common.h | 10 ++
drivers/net/octeontx_ep/otx_ep_ethdev.c | 48 +++++++++
drivers/net/octeontx_ep/otx_ep_vf.c | 128 ++++++++++++++++++++++++
drivers/net/octeontx_ep/otx_ep_vf.h | 4 +
5 files changed, 297 insertions(+)
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c
index 9349e66c0..9703ad023 100644
--- a/drivers/net/octeontx_ep/otx2_ep_vf.c
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c
@@ -190,6 +190,104 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_read32(droq->pkts_sent_reg));
}
+static int
+otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
+ uint64_t reg_val = 0ull;
+
+ /* Resetting doorbells during IQ enabling also to handle abrupt
+ * guest reboot. IQ reset does not clear the doorbells.
+ */
+ otx2_write64(0xFFFFFFFF, otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no));
+
+ while (((otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
+ rte_delay_ms(1);
+ }
+
+ if (!loop) {
+ otx_ep_err("INSTR DBELL not coming back to 0\n");
+ return -EIO;
+ }
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ reg_val |= 0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+
+ otx2_info("IQ[%d] enable done", q_no);
+
+ return 0;
+}
+
+static int
+otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+ reg_val |= 0x1ull;
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+
+ otx2_info("OQ[%d] enable done", q_no);
+
+ return 0;
+}
+
+static int
+otx2_vf_enable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+ int ret;
+
+ for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
+ ret = otx2_vf_enable_iq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++)
+ otx2_vf_enable_oq(otx_ep, q_no);
+
+ return 0;
+}
+
+static void
+otx2_vf_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ /* Reset the doorbell register for this Input Queue. */
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+}
+
+static void
+otx2_vf_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+}
+
+static void
+otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
+ otx2_vf_disable_iq(otx_ep, q_no);
+ otx2_vf_disable_oq(otx_ep, q_no);
+ }
+}
+
static const struct otx_ep_config default_otx2_ep_conf = {
/* IQ attributes */
.iq = {
@@ -249,5 +347,14 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;
+ otx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues;
+ otx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues;
+
+ otx_ep->fn_list.enable_iq = otx2_vf_enable_iq;
+ otx_ep->fn_list.disable_iq = otx2_vf_disable_iq;
+
+ otx_ep->fn_list.enable_oq = otx2_vf_enable_oq;
+ otx_ep->fn_list.disable_oq = otx2_vf_disable_oq;
+
return 0;
}
diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h
index 85fb946b3..51a6750c6 100644
--- a/drivers/net/octeontx_ep/otx_ep_common.h
+++ b/drivers/net/octeontx_ep/otx_ep_common.h
@@ -19,6 +19,7 @@
#define OTX_EP_PCI_RING_ALIGN 65536
#define SDP_PKIND 40
#define SDP_OTX2_PKIND 57
+#define OTX_EP_BUSY_LOOP_COUNT (10000)
#define OTX_EP_MAX_IOQS_PER_VF 8
#define otx_ep_info(fmt, args...) \
@@ -362,7 +363,14 @@ struct otx_ep_fn_list {
int (*setup_device_regs)(struct otx_ep_device *otx_ep);
+ int (*enable_io_queues)(struct otx_ep_device *otx_ep);
void (*disable_io_queues)(struct otx_ep_device *otx_ep);
+
+ int (*enable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);
+ void (*disable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);
+
+ int (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
+ void (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
};
/* SRIOV information */
@@ -417,6 +425,8 @@ struct otx_ep_device {
/* Device configuration */
const struct otx_ep_config *conf;
+ int started;
+
int port_configured;
uint64_t rx_offloads;
diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c
index 33ddc1aed..5fa315e71 100644
--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c
@@ -61,6 +61,50 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
return 0;
}
+static int
+otx_ep_dev_start(struct rte_eth_dev *eth_dev)
+{
+ struct otx_ep_device *otx_epvf;
+ unsigned int q;
+ int ret;
+
+ otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);
+ /* Enable IQ/OQ for this device */
+ ret = otx_epvf->fn_list.enable_io_queues(otx_epvf);
+ if (ret) {
+ otx_ep_err("IOQ enable failed\n");
+ return ret;
+ }
+
+ for (q = 0; q < otx_epvf->nb_rx_queues; q++) {
+ rte_write32(otx_epvf->droq[q]->nb_desc,
+ otx_epvf->droq[q]->pkts_credit_reg);
+
+ rte_wmb();
+ otx_ep_info("OQ[%d] dbells [%d]\n", q,
+ rte_read32(otx_epvf->droq[q]->pkts_credit_reg));
+ }
+
+ otx_epvf->started = 1;
+
+ rte_wmb();
+ otx_ep_info("dev started\n");
+
+ return 0;
+}
+
+/* Stop device and disable input/output functions */
+static int
+otx_ep_dev_stop(struct rte_eth_dev *eth_dev)
+{
+ struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
+
+ otx_epvf->fn_list.disable_io_queues(otx_epvf);
+ otx_epvf->started = 0;
+
+ return 0;
+}
+
static int
otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
{
@@ -308,6 +352,8 @@ otx_ep_tx_queue_release(void *txq)
/* Define our ethernet definitions */
static const struct eth_dev_ops otx_ep_eth_dev_ops = {
.dev_configure = otx_ep_dev_configure,
+ .dev_start = otx_ep_dev_start,
+ .dev_stop = otx_ep_dev_stop,
.rx_queue_setup = otx_ep_rx_queue_setup,
.rx_queue_release = otx_ep_rx_queue_release,
.tx_queue_setup = otx_ep_tx_queue_setup,
@@ -327,6 +373,8 @@ otx_epdev_exit(struct rte_eth_dev *eth_dev)
otx_epvf = OTX_EP_DEV(eth_dev);
+ otx_epvf->fn_list.disable_io_queues(otx_epvf);
+
num_queues = otx_epvf->nb_rx_queues;
for (q = 0; q < num_queues; q++) {
if (otx_ep_delete_oqs(otx_epvf, q)) {
diff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c
index e5a747577..326187fa9 100644
--- a/drivers/net/octeontx_ep/otx_ep_vf.c
+++ b/drivers/net/octeontx_ep/otx_ep_vf.c
@@ -205,6 +205,124 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
}
}
+static int
+otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ uint64_t reg_val = 0ull;
+
+ /* Resetting doorbells during IQ enabling also to handle abrupt
+ * guest reboot. IQ reset does not clear the doorbells.
+ */
+ otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
+ OTX_EP_R_IN_INSTR_DBELL(q_no));
+
+ while (((rte_read64(otx_ep->hw_addr +
+ OTX_EP_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
+ rte_delay_ms(1);
+ }
+
+ if (loop == 0) {
+ otx_ep_err("dbell reset failed\n");
+ return -EIO;
+ }
+
+
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
+ reg_val |= 0x1ull;
+
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
+
+ otx_ep_info("IQ[%d] enable done\n", q_no);
+
+ return 0;
+}
+
+static int
+otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+ uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+
+ /* Resetting doorbells during IQ enabling also to handle abrupt
+ * guest reboot. IQ reset does not clear the doorbells.
+ */
+ otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
+ OTX_EP_R_OUT_SLIST_DBELL(q_no));
+ while (((rte_read64(otx_ep->hw_addr +
+ OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {
+ rte_delay_ms(1);
+ }
+ if (loop == 0) {
+ otx_ep_err("dbell reset failed\n");
+ return -EIO;
+ }
+
+
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
+ reg_val |= 0x1ull;
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
+
+ otx_ep_info("OQ[%d] enable done\n", q_no);
+
+ return 0;
+}
+
+static int
+otx_ep_enable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+ int ret;
+
+ for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
+ ret = otx_ep_enable_iq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) {
+ ret = otx_ep_enable_oq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void
+otx_ep_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ /* Reset the doorbell register for this Input Queue. */
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
+}
+
+static void
+otx_ep_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
+}
+
+static void
+otx_ep_disable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
+ otx_ep_disable_iq(otx_ep, q_no);
+ otx_ep_disable_oq(otx_ep, q_no);
+ }
+}
+
/* OTX_EP default configuration */
static const struct otx_ep_config default_otx_ep_conf = {
/* IQ attributes */
@@ -267,5 +385,15 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)
otx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;
+ otx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues;
+ otx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues;
+
+ otx_ep->fn_list.enable_iq = otx_ep_enable_iq;
+ otx_ep->fn_list.disable_iq = otx_ep_disable_iq;
+
+ otx_ep->fn_list.enable_oq = otx_ep_enable_oq;
+ otx_ep->fn_list.disable_oq = otx_ep_disable_oq;
+
+
return 0;
}
diff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h
index acc16753b..64e4df451 100644
--- a/drivers/net/octeontx_ep/otx_ep_vf.h
+++ b/drivers/net/octeontx_ep/otx_ep_vf.h
@@ -12,6 +12,7 @@
/* OTX_EP VF IQ Registers */
#define OTX_EP_R_IN_CONTROL_START (0x10000)
+#define OTX_EP_R_IN_ENABLE_START (0x10010)
#define OTX_EP_R_IN_INSTR_BADDR_START (0x10020)
#define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030)
#define OTX_EP_R_IN_INSTR_DBELL_START (0x10040)
@@ -21,6 +22,9 @@
#define OTX_EP_R_IN_CONTROL(ring) \
(OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
+#define OTX_EP_R_IN_ENABLE(ring) \
+ (OTX_EP_R_IN_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))
+
#define OTX_EP_R_IN_INSTR_BADDR(ring) \
(OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))
--
2.17.1
next prev parent reply other threads:[~2021-01-26 21:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-26 21:30 [dpdk-dev] [PATCH v3 01/11] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 02/11] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 03/11] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 04/11] net/octeontx_ep: Added basic device setup Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 05/11] net/octeontx_ep: Add dev info get and configure Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 06/11] net/octeontx_ep: Added rxq setup and release Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 07/11] net/octeontx_ep: Added tx queue " Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 08/11] net/octeontx_ep: Setting up iq and oq registers Nalla Pradeep
2021-01-26 21:30 ` Nalla Pradeep [this message]
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 10/11] net/octeontx_ep: Receive data path function added Nalla Pradeep
2021-01-26 21:30 ` [dpdk-dev] [PATCH v3 11/11] net/octeontx_ep: Transmit " Nalla Pradeep
2021-01-27 1:09 ` [dpdk-dev] [PATCH v3 01/11] net/octeontx_ep: add build and doc infrastructure Ferruh Yigit
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