From: Nalla Pradeep <pnalla@marvell.com>
To: Nalla Pradeep <pnalla@marvell.com>,
Radha Mohan Chintakuntla <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH v4 05/11] net/octeontx_ep: Add dev info get and configure
Date: Tue, 26 Jan 2021 13:39:54 -0800 [thread overview]
Message-ID: <20210126214000.57909-5-pnalla@marvell.com> (raw)
In-Reply-To: <20210126214000.57909-1-pnalla@marvell.com>
Add device information get and device configure operations.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/otx_ep_common.h | 15 +++++
drivers/net/octeontx_ep/otx_ep_ethdev.c | 89 ++++++++++++++++++++++++-
drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 +++
3 files changed, 111 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h
diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h
index 74f9e10b1..7f3c913f3 100644
--- a/drivers/net/octeontx_ep/otx_ep_common.h
+++ b/drivers/net/octeontx_ep/otx_ep_common.h
@@ -7,9 +7,12 @@
#define OTX_EP_MAX_RINGS_PER_VF (8)
#define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
#define OTX_EP_64BYTE_INSTR (64)
+#define OTX_EP_MIN_IQ_DESCRIPTORS (128)
+#define OTX_EP_MIN_OQ_DESCRIPTORS (128)
#define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
#define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
#define OTX_EP_OQ_BUF_SIZE (2048)
+#define OTX_EP_MIN_RX_BUF_SIZE (64)
#define OTX_EP_OQ_INFOPTR_MODE (0)
#define OTX_EP_OQ_REFIL_THRESHOLD (16)
@@ -112,6 +115,10 @@ struct otx_ep_device {
struct otx_ep_fn_list fn_list;
+ uint32_t max_tx_queues;
+
+ uint32_t max_rx_queues;
+
/* SR-IOV info */
struct otx_ep_sriov_info sriov_info;
@@ -119,7 +126,15 @@ struct otx_ep_device {
const struct otx_ep_config *conf;
int port_configured;
+
+ uint64_t rx_offloads;
+
+ uint64_t tx_offloads;
};
+#define OTX_EP_MAX_PKT_SZ 64000U
+
+#define OTX_EP_MAX_MAC_ADDRS 1
+
extern int otx_net_ep_logtype;
#endif /* _OTX_EP_COMMON_H_ */
diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c
index c90ef13c0..4b6800fae 100644
--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c
@@ -10,8 +10,57 @@
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
#include "otx2_ep_vf.h"
+#include "otx_ep_rxtx.h"
+
+#define OTX_EP_DEV(_eth_dev) \
+ ((struct otx_ep_device *)(_eth_dev)->data->dev_private)
+
+static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {
+ .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS,
+ .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS,
+ .nb_align = OTX_EP_RXD_ALIGN,
+};
+
+static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {
+ .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS,
+ .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS,
+ .nb_align = OTX_EP_TXD_ALIGN,
+};
+
+static int
+otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *devinfo)
+{
+ struct otx_ep_device *otx_epvf;
+ struct rte_pci_device *pdev;
+ uint32_t dev_id;
+
+ otx_epvf = OTX_EP_DEV(eth_dev);
+ pdev = otx_epvf->pdev;
+ dev_id = pdev->id.device_id;
+
+ devinfo->speed_capa = ETH_LINK_SPEED_10G;
+ devinfo->max_rx_queues = otx_epvf->max_rx_queues;
+ devinfo->max_tx_queues = otx_epvf->max_tx_queues;
+
+ devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
+ if (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||
+ dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
+ dev_id == PCI_DEVID_CN98XX_EP_NET_VF) {
+ devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
+ devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;
+ devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;
+ devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;
+ }
+
+ devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;
+
+ devinfo->rx_desc_lim = otx_ep_rx_desc_lim;
+ devinfo->tx_desc_lim = otx_ep_tx_desc_lim;
+
+ return 0;
+}
-#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
static int
otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
{
@@ -62,6 +111,41 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
return -ENOMEM;
}
+static int
+otx_ep_dev_configure(struct rte_eth_dev *eth_dev)
+{
+ struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct rte_eth_rxmode *rxmode;
+ struct rte_eth_txmode *txmode;
+ struct rte_eth_conf *conf;
+ uint32_t ethdev_queues;
+
+ conf = &data->dev_conf;
+ rxmode = &conf->rxmode;
+ txmode = &conf->txmode;
+ ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
+ if (eth_dev->data->nb_rx_queues > ethdev_queues ||
+ eth_dev->data->nb_tx_queues > ethdev_queues) {
+ otx_ep_err("invalid num queues\n");
+ return -ENOMEM;
+ }
+ otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n",
+ eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);
+
+ otx_epvf->port_configured = 1;
+ otx_epvf->rx_offloads = rxmode->offloads;
+ otx_epvf->tx_offloads = txmode->offloads;
+
+ return 0;
+}
+
+/* Define our ethernet definitions */
+static const struct eth_dev_ops otx_ep_eth_dev_ops = {
+ .dev_configure = otx_ep_dev_configure,
+ .dev_infos_get = otx_ep_dev_info_get,
+};
+
static int
otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
{
@@ -99,6 +183,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
}
otx_epvf->eth_dev = eth_dev;
otx_epvf->port_id = eth_dev->data->port_id;
+ eth_dev->dev_ops = &otx_ep_eth_dev_ops;
eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
if (eth_dev->data->mac_addrs == NULL) {
otx_ep_err("MAC addresses memory allocation failed\n");
@@ -139,8 +224,6 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = {
{ .vendor_id = 0, /* sentinel */ }
};
-
-
static struct rte_pci_driver rte_otx_ep_pmd = {
.id_table = pci_id_otx_ep_map,
.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
diff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.h b/drivers/net/octeontx_ep/otx_ep_rxtx.h
new file mode 100644
index 000000000..9779e96b6
--- /dev/null
+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _OTX_EP_RXTX_H_
+#define _OTX_EP_RXTX_H_
+
+#define OTX_EP_RXD_ALIGN 1
+#define OTX_EP_TXD_ALIGN 1
+#endif
--
2.17.1
next prev parent reply other threads:[~2021-01-26 21:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-26 21:39 [dpdk-dev] [PATCH v4 01/11] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 02/11] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 03/11] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 04/11] net/octeontx_ep: Added basic device setup Nalla Pradeep
2021-01-26 21:39 ` Nalla Pradeep [this message]
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 06/11] net/octeontx_ep: Added rxq setup and release Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 07/11] net/octeontx_ep: Added tx queue " Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 08/11] net/octeontx_ep: Setting up iq and oq registers Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 09/11] net/octeontx_ep: Added dev start and stop Nalla Pradeep
2021-01-26 21:39 ` [dpdk-dev] [PATCH v4 10/11] net/octeontx_ep: Receive data path function added Nalla Pradeep
2021-01-26 21:40 ` [dpdk-dev] [PATCH v4 11/11] net/octeontx_ep: Transmit " Nalla Pradeep
2021-01-27 10:56 ` [dpdk-dev] [PATCH v4 01/11] net/octeontx_ep: add build and doc infrastructure Ferruh Yigit
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