From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97696A052A; Wed, 27 Jan 2021 17:13:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 17826140F1C; Wed, 27 Jan 2021 17:10:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C189B140F09 for ; Wed, 27 Jan 2021 17:10:30 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10RG6q4r017546; Wed, 27 Jan 2021 08:10:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=RWu0UPOABleYC+9s0AphKHqU6i0rcJIp2UKw0tR+veg=; b=DzOVGijA4nXRJSrDOdjKdvW72RTHWrB2W34k3xGD0TSD5VtYKSLJfnH/GnL65lP0gW6u uXItIMXICh8HkERS3ZTY5od8VvG2/24jIYgVGwUzSbs8KlecB5ZFxBFR8PB4kry/YEVu 8FrI3ZZ2uUt5DRp2pgP4cxv5EjS+zxGN9wtnFLqvao82qAMaJ8TACb/3RSyymC4KHuYn oKVWTpvL4rppcmieims+GjLAUHUtdN6c52MHmqRMSADGs3oMG/Bwgq+yvLY8Rhc1bK5W ze6I3bHUrCRDhFFf6YH6y3u6gCWLDxnhBI1WHjAYEXOPDlJpWuMyPIYFFle9If4QVaRz WA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 36b1xphftd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Jan 2021 08:10:29 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 08:10:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 08:10:27 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Jan 2021 08:10:25 -0800 From: To: , CC: , Yuri Chipchev , Liron Himi Date: Wed, 27 Jan 2021 18:09:28 +0200 Message-ID: <20210127160948.6008-15-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210127160948.6008-1-lironh@marvell.com> References: <20210122191925.24308-1-lironh@marvell.com> <20210127160948.6008-1-lironh@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-27_05:2021-01-27, 2021-01-27 signatures=0 Subject: [dpdk-dev] [PATCH v3 14/34] net/mvpp2: add Tx flow control X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev Add tx flow control operations. Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 59 ++++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 8 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index db097ef64a..eb0bfcab2e 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2033,6 +2033,19 @@ mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; + ret = pp2_ppio_get_tx_pause(priv->ppio, &en); + if (ret) { + MRVL_LOG(ERR, "Failed to read tx pause state"); + return ret; + } + + if (en) { + if (fc_conf->mode == RTE_FC_NONE) + fc_conf->mode = RTE_FC_TX_PAUSE; + else + fc_conf->mode = RTE_FC_FULL; + } + return 0; } @@ -2051,6 +2064,9 @@ static int mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct mrvl_priv *priv = dev->data->dev_private; + struct pp2_ppio_tx_pause_params mrvl_pause_params; + int ret; + int rx_en, tx_en; if (!priv) return -EPERM; @@ -2065,16 +2081,43 @@ mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return -EINVAL; } - if (fc_conf->mode == RTE_FC_NONE || - fc_conf->mode == RTE_FC_RX_PAUSE) { - int ret, en; + switch (fc_conf->mode) { + case RTE_FC_FULL: + rx_en = 1; + tx_en = 1; + break; + case RTE_FC_TX_PAUSE: + rx_en = 0; + tx_en = 1; + break; + case RTE_FC_RX_PAUSE: + rx_en = 1; + tx_en = 0; + break; + case RTE_FC_NONE: + rx_en = 0; + tx_en = 0; + break; + default: + MRVL_LOG(ERR, "Incorrect Flow control flag (%d)", + fc_conf->mode); + return -EINVAL; + } - en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; - ret = pp2_ppio_set_rx_pause(priv->ppio, en); - if (ret) - MRVL_LOG(ERR, - "Failed to change flowctrl on RX side"); + /* Set RX flow control */ + ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en); + if (ret) { + MRVL_LOG(ERR, "Failed to change RX flowctrl"); + return ret; + } + /* Set TX flow control */ + mrvl_pause_params.en = tx_en; + /* all inqs participate in xon/xoff decision */ + mrvl_pause_params.use_tc_pause_inqs = 0; + ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params); + if (ret) { + MRVL_LOG(ERR, "Failed to change TX flowctrl"); return ret; } -- 2.28.0