From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC83EA052A; Wed, 27 Jan 2021 17:15:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0ACA5140F5C; Wed, 27 Jan 2021 17:10:55 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 344C7140F31 for ; Wed, 27 Jan 2021 17:10:50 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10RG5dYn027128; Wed, 27 Jan 2021 08:10:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=u9PzXxnX/tzBWsuz6RjKC+MUv6rnU6lTZ73Q6IO+qf4=; b=DZOg5tJQ130Mx334l+WEJMr76DKKZSR0mW5VSOJAiYnx1HK+DRnBqjfjSi2UrgI6cX0X nEx3lWpgF5sspaxVLes1Fy/r3myUEqZZvOQfpqyc5xPw3yfYoY51gwAn/XdVe7AXtPOj fT1W9+V52I+1AgSiKVTjBxBkshN1r15L5Ezw76kC6NV3FQ5XUKxxTRvfLV4YG6ORn/SG C80Za4Q7Rxvt9VHgbh8QziCImXM6qlY9ben7LItRTQ4L3PwVzcfXfwe6tAnt6MJd0RFX O9+n3/mX2kMyYVAkXbcRzybV3jBMcXh2pSn/QIvImRgKI6nFI03XO1A2v6A95Lvb/V5w TA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 368j1uc3a8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Jan 2021 08:10:49 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 08:10:48 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 08:10:47 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Jan 2021 08:10:46 -0800 From: To: , CC: , Liron Himi Date: Wed, 27 Jan 2021 18:09:38 +0200 Message-ID: <20210127160948.6008-25-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210127160948.6008-1-lironh@marvell.com> References: <20210122191925.24308-1-lironh@marvell.com> <20210127160948.6008-1-lironh@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-27_05:2021-01-27, 2021-01-27 signatures=0 Subject: [dpdk-dev] [PATCH v3 24/34] net/mvpp2: introduce fixup for fifo overrun X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi Currently the HW is configured with only one pool which its buffer size may be larger than the rx-fifo-size. In that situation, frame size larger than the fifo-size is gets dropped due to fifo overrun. this is cause because the HW works in cut-through mode which waits to have in the fifo at least the amount of bytes as define in the smallest pool's buffer size. This patch add a dummy pool which its buffer size is very small (smaller than 64B frame). this tricks the HW and any frame size is gets passed from the FIFO to the PP2. Signed-off-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 92 +++++++++++++++++++++++++++------ drivers/net/mvpp2/mrvl_ethdev.h | 2 + drivers/net/mvpp2/mrvl_qos.c | 1 + 3 files changed, 80 insertions(+), 15 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index b7211b95fe..5f814f168f 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -90,6 +90,8 @@ static int used_bpools[PP2_NUM_PKT_PROC] = { static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; +static int dummy_pool_id[PP2_NUM_PKT_PROC]; +struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0}; struct mrvl_ifnames { const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; @@ -189,6 +191,52 @@ static struct { MRVL_XSTATS_TBL_ENTRY(tx_errors) }; +static inline int +mrvl_reserve_bit(int *bitmap, int max) +{ + int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); + + if (n >= max) + return -1; + + *bitmap |= 1 << n; + + return n; +} + +static int +mrvl_pp2_fixup_init(void) +{ + struct pp2_bpool_params bpool_params; + char name[15]; + int err, i; + + memset(dummy_pool, 0, sizeof(dummy_pool)); + for (i = 0; i < pp2_get_num_inst(); i++) { + dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i], + PP2_BPOOL_NUM_POOLS); + if (dummy_pool_id[i] < 0) { + MRVL_LOG(ERR, "Can't find free pool\n"); + return -1; + } + + memset(name, 0, sizeof(name)); + snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]); + memset(&bpool_params, 0, sizeof(bpool_params)); + bpool_params.match = name; + bpool_params.buff_len = MRVL_PKT_OFFS; + bpool_params.dummy_short_pool = 1; + err = pp2_bpool_init(&bpool_params, &dummy_pool[i]); + if (err != 0 || !dummy_pool[i]) { + MRVL_LOG(ERR, "BPool init failed!\n"); + used_bpools[i] &= ~(1 << dummy_pool_id[i]); + return -1; + } + } + + return 0; +} + /** * Initialize packet processor. * @@ -198,7 +246,8 @@ static struct { static int mrvl_init_pp2(void) { - struct pp2_init_params init_params; + struct pp2_init_params init_params; + int err; memset(&init_params, 0, sizeof(init_params)); init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; @@ -207,7 +256,32 @@ mrvl_init_pp2(void) if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, sizeof(struct pp2_parse_udfs)); - return pp2_init(&init_params); + err = pp2_init(&init_params); + if (err != 0) { + MRVL_LOG(ERR, "PP2 init failed"); + return -1; + } + + err = mrvl_pp2_fixup_init(); + if (err != 0) { + MRVL_LOG(ERR, "PP2 fixup init failed"); + return -1; + } + + return 0; +} + +static void +mrvl_pp2_fixup_deinit(void) +{ + int i; + + for (i = 0; i < PP2_NUM_PKT_PROC; i++) { + if (!dummy_pool[i]) + continue; + pp2_bpool_deinit(dummy_pool[i]); + used_bpools[i] &= ~(1 << dummy_pool_id[i]); + } } /** @@ -219,6 +293,7 @@ mrvl_init_pp2(void) static void mrvl_deinit_pp2(void) { + mrvl_pp2_fixup_deinit(); pp2_deinit(); } @@ -275,19 +350,6 @@ mrvl_get_bpool_size(int pp2_id, int pool_id) return size; } -static inline int -mrvl_reserve_bit(int *bitmap, int max) -{ - int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); - - if (n >= max) - return -1; - - *bitmap |= 1 << n; - - return n; -} - static int mrvl_init_hif(int core_id) { diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index 27d34ecfe0..b0cdddd15e 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -196,6 +196,8 @@ extern int mrvl_logtype; rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ __func__, ##args) +extern struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC]; + /** * Convert string to uint32_t with extra checks for result correctness. * diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 310fd73840..a3add540b8 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -881,6 +881,7 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs, param->pkt_offset = MRVL_PKT_OFFS; param->pools[0][0] = bpool; + param->pools[0][1] = dummy_pool[bpool->pp2_id]; param->default_color = color; inq_params = rte_zmalloc_socket("inq_params", -- 2.28.0