From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BBA1A09E4; Thu, 28 Jan 2021 16:23:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87D261889EA; Thu, 28 Jan 2021 16:23:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 779B44067A for ; Thu, 28 Jan 2021 16:23:32 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10SFKYt5014565; Thu, 28 Jan 2021 07:23:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=GaQhB0wwf0CZINCadfqJZL4KdI9+6QOaBV0KwW5uNV0=; b=W2GM2qM7bAbY9/5wOcGDE94WVMO0gCxD93KIKTcdtWgiTUok7FrJHoX9U4N7wWLSvoPX FB7fKxqtTegPpjg4MR8/rzTQB19ii4ID3MbWB1vKW0v+CxofX26FKoXmQehgm4kYdZGo VJPfxjMNRAcjYZmJDKMJJScHE2mcECdbwv5FQL7TLPSFO4luaQogteB9owMsVmvrB5vO OZPKeyx5ZXMtRD3uCqdOTCA6zaZFl80tcvjNKIy9vBNOnA04odsjIkK4XnjPZ8BnkRTB sonGPmeoPUFZ3AnqGg4TRLzc38rzsu2qbgxC8hXLaBh9OSQKnzzaunyLbW0ALiZx3xbl BQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 368j1ufcns-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 28 Jan 2021 07:23:31 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 07:23:30 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 07:23:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 07:23:29 -0800 Received: from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196]) by maili.marvell.com (Postfix) with ESMTP id 9783B3F703F; Thu, 28 Jan 2021 07:23:29 -0800 (PST) From: Nalla Pradeep To: Jerin Jacob , Nithin Dabilpuram , Nalla Pradeep , "Radha Mohan Chintakuntla" , Veerasenareddy Burru , Anatoly Burakov CC: , Date: Thu, 28 Jan 2021 07:22:12 -0800 Message-ID: <20210128152220.214485-4-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118093602.5449-1-pnalla@marvell.com> References: <20210118093602.5449-1-pnalla@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-28_11:2021-01-28, 2021-01-28 signatures=0 Subject: [dpdk-dev] [PATCH v5 03/11] net/octeontx_ep: add device init and uninit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add basic init and uninit function which includes initializing fields of ethdev private structure. Signed-off-by: Nalla Pradeep --- drivers/common/octeontx2/otx2_common.h | 2 +- drivers/net/octeontx_ep/otx_ep_common.h | 19 ++++++- drivers/net/octeontx_ep/otx_ep_ethdev.c | 72 +++++++++++++++++++++++-- 3 files changed, 86 insertions(+), 7 deletions(-) diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h index 96021eda2..cd52e098e 100644 --- a/drivers/common/octeontx2/otx2_common.h +++ b/drivers/common/octeontx2/otx2_common.h @@ -136,7 +136,7 @@ extern int otx2_logtype_ree; #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081 -#define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */ +#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */ /* OCTEON TX2 98xx EP mode */ #define PCI_DEVID_CN98XX_EP_NET_VF 0xB103 #define PCI_DEVID_OCTEONTX2_EP_RAW_VF 0xB204 /* OCTEON TX2 EP mode */ diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 35ea99a79..0d6484c87 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -4,11 +4,28 @@ #ifndef _OTX_EP_COMMON_H_ #define _OTX_EP_COMMON_H_ +#define otx_ep_info(fmt, args...) \ + RTE_LOG(INFO, PMD, fmt "\n", ## args) + +#define otx_ep_err(fmt, args...) \ + RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", \ + __func__, __LINE__, ## args) + +#define otx_ep_dbg(fmt, args...) \ + rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \ + "%s():%u " fmt "\n", \ + __func__, __LINE__, ##args) + /* OTX_EP EP VF device data structure */ struct otx_ep_device { /* PCI device pointer */ struct rte_pci_device *pdev; - + uint16_t chip_id; struct rte_eth_dev *eth_dev; + int port_id; + /* Memory mapped h/w address */ + uint8_t *hw_addr; }; + +extern int otx_net_ep_logtype; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index fc4356013..07cf07464 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -8,20 +8,81 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" +#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) static int -otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) +otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = otx_epvf->pdev; + uint32_t dev_id = pdev->id.device_id; + int ret = 0; - return -ENODEV; + switch (dev_id) { + case PCI_DEVID_OCTEONTX_EP_VF: + otx_epvf->chip_id = dev_id; + break; + case PCI_DEVID_OCTEONTX2_EP_NET_VF: + case PCI_DEVID_CN98XX_EP_NET_VF: + otx_epvf->chip_id = dev_id; + break; + default: + otx_ep_err("Unsupported device\n"); + ret = -EINVAL; + } + + if (!ret) + otx_ep_info("OTX_EP dev_id[%d]\n", dev_id); + + return ret; +} + +/* OTX_EP VF device initialization */ +static int +otx_epdev_init(struct otx_ep_device *otx_epvf) +{ + int ret = 0; + + ret = otx_ep_chip_specific_setup(otx_epvf); + if (ret) { + otx_ep_err("Chip specific setup failed\n"); + goto setup_fail; + } + +setup_fail: + return ret; +} + +static int +otx_ep_eth_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev) +{ + return 0; } static int otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + struct rte_ether_addr vf_mac_addr; + + /* Single process support */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + otx_epvf->eth_dev = eth_dev; + otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) { + otx_ep_err("MAC addresses memory allocation failed\n"); + return -ENOMEM; + } + rte_eth_random_addr(vf_mac_addr.addr_bytes); + rte_ether_addr_copy(eth_dev->data->mac_addrs, &vf_mac_addr); + otx_epvf->hw_addr = pdev->mem_resource[0].addr; + otx_epvf->pdev = pdev; + + otx_epdev_init(otx_epvf); - return -ENODEV; + return 0; } static int @@ -43,6 +104,7 @@ otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev) /* Set of PCI devices this driver supports */ static const struct rte_pci_id pci_id_otx_ep_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) }, { .vendor_id = 0, /* sentinel */ } }; -- 2.17.1