From: Nalla Pradeep <pnalla@marvell.com>
To: Nalla Pradeep <pnalla@marvell.com>,
Radha Mohan Chintakuntla <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH v7 05/12] net/octeontx_ep: added basic device setup
Date: Fri, 29 Jan 2021 04:45:03 -0800 [thread overview]
Message-ID: <20210129124510.12158-6-pnalla@marvell.com> (raw)
In-Reply-To: <20210129001640.1251-1-pnalla@marvell.com>
Functions to setup device, basic input queue and output queue registers
are added.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/meson.build | 2 +
drivers/net/octeontx_ep/otx2_ep_vf.c | 131 +++++++++++++++++++++
drivers/net/octeontx_ep/otx2_ep_vf.h | 11 ++
drivers/net/octeontx_ep/otx_ep_common.h | 92 +++++++++++++++
drivers/net/octeontx_ep/otx_ep_ethdev.c | 7 ++
drivers/net/octeontx_ep/otx_ep_vf.c | 148 ++++++++++++++++++++++++
drivers/net/octeontx_ep/otx_ep_vf.h | 33 ++++++
7 files changed, 424 insertions(+)
create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.c
create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.h
create mode 100644 drivers/net/octeontx_ep/otx_ep_vf.c
diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build
index 73e04b0be..8cd2e76d1 100644
--- a/drivers/net/octeontx_ep/meson.build
+++ b/drivers/net/octeontx_ep/meson.build
@@ -5,6 +5,8 @@
deps += ['common_octeontx2']
sources = files(
'otx_ep_ethdev.c',
+ 'otx_ep_vf.c',
+ 'otx2_ep_vf.c',
)
includes += include_directories('../../common/octeontx2')
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c
new file mode 100644
index 000000000..6368ddc80
--- /dev/null
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "otx2_common.h"
+#include "otx_ep_common.h"
+#include "otx2_ep_vf.h"
+
+static void
+otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
+ * IS_64B is by default enabled.
+ */
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
+
+ reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
+ reg_val |= SDP_VF_R_IN_CTL_IS_64B;
+ reg_val |= SDP_VF_R_IN_CTL_ESR;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
+}
+
+static void
+otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
+
+ reg_val &= ~(SDP_VF_R_OUT_CTL_IMODE);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
+ reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
+
+ /* INFO/DATA ptr swap is required */
+ reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
+}
+
+static void
+otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
+{
+ uint64_t q_no = 0ull;
+
+ for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
+ otx2_vf_setup_global_iq_reg(otx_ep, q_no);
+}
+
+static void
+otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no;
+
+ for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
+ otx2_vf_setup_global_oq_reg(otx_ep, q_no);
+}
+
+static void
+otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)
+{
+ otx2_vf_setup_global_input_regs(otx_ep);
+ otx2_vf_setup_global_output_regs(otx_ep);
+}
+
+static const struct otx_ep_config default_otx2_ep_conf = {
+ /* IQ attributes */
+ .iq = {
+ .max_iqs = OTX_EP_CFG_IO_QUEUES,
+ .instr_type = OTX_EP_64BYTE_INSTR,
+ .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
+ OTX_EP_CFG_IO_QUEUES),
+ },
+
+ /* OQ attributes */
+ .oq = {
+ .max_oqs = OTX_EP_CFG_IO_QUEUES,
+ .info_ptr = OTX_EP_OQ_INFOPTR_MODE,
+ .refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
+ },
+
+ .num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
+ .num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
+ .oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
+};
+
+static const struct otx_ep_config*
+otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
+{
+ const struct otx_ep_config *default_conf = NULL;
+
+ default_conf = &default_otx2_ep_conf;
+
+ return default_conf;
+}
+
+int
+otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
+{
+ uint64_t reg_val = 0ull;
+
+ /* If application doesn't provide its conf, use driver default conf */
+ if (otx_ep->conf == NULL) {
+ otx_ep->conf = otx2_ep_get_defconf(otx_ep);
+ if (otx_ep->conf == NULL) {
+ otx2_err("SDP VF default config not found");
+ return -ENOENT;
+ }
+ otx2_info("Default config is used");
+ }
+
+ /* Get IOQs (RPVF] count */
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(0));
+
+ otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
+ & SDP_VF_R_IN_CTL_RPVF_MASK);
+
+ otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
+
+ otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;
+
+ return 0;
+}
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h
new file mode 100644
index 000000000..191fee426
--- /dev/null
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#ifndef _OTX2_EP_VF_H_
+#define _OTX2_EP_VF_H_
+
+int
+otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
+
+#endif /*_OTX2_EP_VF_H_ */
+
diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h
index 9bf14540b..c138c2dc7 100644
--- a/drivers/net/octeontx_ep/otx_ep_common.h
+++ b/drivers/net/octeontx_ep/otx_ep_common.h
@@ -4,6 +4,16 @@
#ifndef _OTX_EP_COMMON_H_
#define _OTX_EP_COMMON_H_
+#define OTX_EP_MAX_RINGS_PER_VF (8)
+#define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
+#define OTX_EP_64BYTE_INSTR (64)
+#define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
+#define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
+#define OTX_EP_OQ_BUF_SIZE (2048)
+
+#define OTX_EP_OQ_INFOPTR_MODE (0)
+#define OTX_EP_OQ_REFIL_THRESHOLD (16)
+
#define otx_ep_info(fmt, args...) \
rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \
"%s():%u " fmt "\n", \
@@ -19,15 +29,97 @@
"%s():%u " fmt "\n", \
__func__, __LINE__, ##args)
+#define otx_ep_write64(value, base_addr, reg_off) \
+ {\
+ typeof(value) val = (value); \
+ typeof(reg_off) off = (reg_off); \
+ otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \
+ (unsigned long)off, (unsigned long long)val); \
+ rte_write64(val, ((base_addr) + off)); \
+ }
+
+struct otx_ep_device;
+
+/* Structure to define the configuration attributes for each Input queue. */
+struct otx_ep_iq_config {
+ /* Max number of IQs available */
+ uint16_t max_iqs;
+
+ /* Command size - 32 or 64 bytes */
+ uint16_t instr_type;
+
+ /* Pending list size, usually set to the sum of the size of all IQs */
+ uint32_t pending_list_size;
+};
+
+/* Structure to define the configuration attributes for each Output queue. */
+struct otx_ep_oq_config {
+ /* Max number of OQs available */
+ uint16_t max_oqs;
+
+ /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
+ uint16_t info_ptr;
+
+ /** The number of buffers that were consumed during packet processing by
+ * the driver on this Output queue before the driver attempts to
+ * replenish the descriptor ring with new buffers.
+ */
+ uint32_t refill_threshold;
+};
+
+/* Structure to define the configuration. */
+struct otx_ep_config {
+ /* Input Queue attributes. */
+ struct otx_ep_iq_config iq;
+
+ /* Output Queue attributes. */
+ struct otx_ep_oq_config oq;
+
+ /* Num of desc for IQ rings */
+ uint32_t num_iqdef_descs;
+
+ /* Num of desc for OQ rings */
+ uint32_t num_oqdef_descs;
+
+ /* OQ buffer size */
+ uint32_t oqdef_buf_size;
+};
+
+/* SRIOV information */
+struct otx_ep_sriov_info {
+ /* Number of rings assigned to VF */
+ uint32_t rings_per_vf;
+
+ /* Number of VF devices enabled */
+ uint32_t num_vfs;
+};
+
+/* Required functions for each VF device */
+struct otx_ep_fn_list {
+ void (*setup_device_regs)(struct otx_ep_device *otx_ep);
+};
+
/* OTX_EP EP VF device data structure */
struct otx_ep_device {
/* PCI device pointer */
struct rte_pci_device *pdev;
+
uint16_t chip_id;
+
struct rte_eth_dev *eth_dev;
+
int port_id;
+
/* Memory mapped h/w address */
uint8_t *hw_addr;
+
+ struct otx_ep_fn_list fn_list;
+
+ /* SR-IOV info */
+ struct otx_ep_sriov_info sriov_info;
+
+ /* Device configuration */
+ const struct otx_ep_config *conf;
};
extern int otx_net_ep_logtype;
diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c
index c672021e8..feb1335dd 100644
--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c
@@ -7,6 +7,7 @@
#include "otx2_common.h"
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
+#include "otx2_ep_vf.h"
#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
static int
@@ -19,10 +20,12 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
switch (dev_id) {
case PCI_DEVID_OCTEONTX_EP_VF:
otx_epvf->chip_id = dev_id;
+ ret = otx_ep_vf_setup_device(otx_epvf);
break;
case PCI_DEVID_OCTEONTX2_EP_NET_VF:
case PCI_DEVID_CN98XX_EP_NET_VF:
otx_epvf->chip_id = dev_id;
+ ret = otx2_ep_vf_setup_device(otx_epvf);
break;
default:
otx_ep_err("Unsupported device\n");
@@ -47,6 +50,10 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
goto setup_fail;
}
+ otx_epvf->fn_list.setup_device_regs(otx_epvf);
+
+ otx_ep_info("OTX_EP Device is Ready\n");
+
setup_fail:
return ret;
}
diff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c
new file mode 100644
index 000000000..9aeb161ff
--- /dev/null
+++ b/drivers/net/octeontx_ep/otx_ep_vf.c
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_common.h>
+#include <rte_cycles.h>
+#include <rte_ethdev_driver.h>
+#include <rte_ethdev_pci.h>
+#include <rte_io.h>
+
+#include "otx_ep_common.h"
+#include "otx_ep_vf.h"
+
+
+static void
+otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
+ * IS_64B is by default enabled.
+ */
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
+
+ reg_val |= OTX_EP_R_IN_CTL_RDSIZE;
+ reg_val |= OTX_EP_R_IN_CTL_IS_64B;
+ reg_val |= OTX_EP_R_IN_CTL_ESR;
+
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_CONTROL(q_no));
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
+
+ if (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {
+ do {
+ reg_val = rte_read64(otx_ep->hw_addr +
+ OTX_EP_R_IN_CONTROL(q_no));
+ } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
+ }
+}
+
+static void
+otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(q_no));
+
+ reg_val &= ~(OTX_EP_R_OUT_CTL_IMODE);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_P);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_P);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_I);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_I);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_ES_I);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_D);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_D);
+ reg_val &= ~(OTX_EP_R_OUT_CTL_ES_D);
+
+ /* INFO/DATA ptr swap is required */
+ reg_val |= (OTX_EP_R_OUT_CTL_ES_P);
+
+ otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));
+}
+
+static void
+otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)
+{
+ uint64_t q_no = 0ull;
+
+ for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
+ otx_ep_setup_global_iq_reg(otx_ep, q_no);
+}
+
+static void
+otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no;
+
+ for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
+ otx_ep_setup_global_oq_reg(otx_ep, q_no);
+}
+
+static void
+otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)
+{
+ otx_ep_setup_global_input_regs(otx_ep);
+ otx_ep_setup_global_output_regs(otx_ep);
+}
+
+/* OTX_EP default configuration */
+static const struct otx_ep_config default_otx_ep_conf = {
+ /* IQ attributes */
+ .iq = {
+ .max_iqs = OTX_EP_CFG_IO_QUEUES,
+ .instr_type = OTX_EP_64BYTE_INSTR,
+ .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
+ OTX_EP_CFG_IO_QUEUES),
+ },
+
+ /* OQ attributes */
+ .oq = {
+ .max_oqs = OTX_EP_CFG_IO_QUEUES,
+ .info_ptr = OTX_EP_OQ_INFOPTR_MODE,
+ .refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
+ },
+
+ .num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
+ .num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
+ .oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
+
+};
+
+
+static const struct otx_ep_config*
+otx_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
+{
+ const struct otx_ep_config *default_conf = NULL;
+
+ default_conf = &default_otx_ep_conf;
+
+ return default_conf;
+}
+
+int
+otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)
+{
+ uint64_t reg_val = 0ull;
+
+ /* If application doesn't provide its conf, use driver default conf */
+ if (otx_ep->conf == NULL) {
+ otx_ep->conf = otx_ep_get_defconf(otx_ep);
+ if (otx_ep->conf == NULL) {
+ otx_ep_err("OTX_EP VF default config not found\n");
+ return -ENOENT;
+ }
+ otx_ep_info("Default config is used\n");
+ }
+
+ /* Get IOQs (RPVF] count */
+ reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(0));
+
+ otx_ep->sriov_info.rings_per_vf = ((reg_val >> OTX_EP_R_IN_CTL_RPVF_POS)
+ & OTX_EP_R_IN_CTL_RPVF_MASK);
+
+ otx_ep_info("OTX_EP RPVF: %d\n", otx_ep->sriov_info.rings_per_vf);
+
+ otx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;
+
+ return 0;
+}
diff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h
index e88b40971..c5741a3f1 100644
--- a/drivers/net/octeontx_ep/otx_ep_vf.h
+++ b/drivers/net/octeontx_ep/otx_ep_vf.h
@@ -4,6 +4,39 @@
#ifndef _OTX_EP_VF_H_
#define _OTX_EP_VF_H_
+#define OTX_EP_RING_OFFSET (0x1ull << 17)
+
+/* OTX_EP VF IQ Registers */
+#define OTX_EP_R_IN_CONTROL_START (0x10000)
+#define OTX_EP_R_IN_CONTROL(ring) \
+ (OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
+
+/* OTX_EP VF IQ Masks */
+#define OTX_EP_R_IN_CTL_RPVF_MASK (0xF)
+#define OTX_EP_R_IN_CTL_RPVF_POS (48)
+
+#define OTX_EP_R_IN_CTL_IDLE (0x1ull << 28)
+#define OTX_EP_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
+#define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24)
+#define OTX_EP_R_IN_CTL_ESR (0x1ull << 1)
+/* OTX_EP VF OQ Registers */
+#define OTX_EP_R_OUT_CONTROL_START (0x10150)
+#define OTX_EP_R_OUT_CONTROL(ring) \
+ (OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
+/* OTX_EP VF OQ Masks */
+#define OTX_EP_R_OUT_CTL_ES_I (1ull << 34)
+#define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33)
+#define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32)
+#define OTX_EP_R_OUT_CTL_ES_D (1ull << 30)
+#define OTX_EP_R_OUT_CTL_NSR_D (1ull << 29)
+#define OTX_EP_R_OUT_CTL_ROR_D (1ull << 28)
+#define OTX_EP_R_OUT_CTL_ES_P (1ull << 26)
+#define OTX_EP_R_OUT_CTL_NSR_P (1ull << 25)
+#define OTX_EP_R_OUT_CTL_ROR_P (1ull << 24)
+#define OTX_EP_R_OUT_CTL_IMODE (1ull << 23)
+
#define PCI_DEVID_OCTEONTX_EP_VF 0xa303
+int
+otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);
#endif /*_OTX_EP_VF_H_ */
--
2.17.1
next prev parent reply other threads:[~2021-01-29 12:45 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 9:35 [dpdk-dev] [PATCH v2 01/11] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 02/11] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-19 11:55 ` Jerin Jacob
2021-01-26 15:27 ` Ferruh Yigit
2021-01-27 11:45 ` [dpdk-dev] [EXT] " Pradeep Kumar Nalla
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 03/11] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-19 12:06 ` Jerin Jacob
2021-01-26 15:25 ` Ferruh Yigit
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 04/11] net/octeontx_ep: Added basic device setup Nalla Pradeep
2021-01-19 12:09 ` Jerin Jacob
2021-01-26 15:29 ` Ferruh Yigit
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 05/11] net/octeontx_ep: Add dev info get and configure Nalla Pradeep
2021-01-26 15:31 ` Ferruh Yigit
2021-01-28 7:03 ` [dpdk-dev] [EXT] " Pradeep Kumar Nalla
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 06/11] net/octeontx_ep: Added rxq setup and release Nalla Pradeep
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 07/11] net/octeontx_ep: Added tx queue " Nalla Pradeep
2021-01-18 9:35 ` [dpdk-dev] [PATCH v2 08/11] net/octeontx_ep: Setting up iq and oq registers Nalla Pradeep
2021-01-26 15:32 ` Ferruh Yigit
2021-01-18 9:36 ` [dpdk-dev] [PATCH v2 09/11] net/octeontx_ep: Added dev start and stop Nalla Pradeep
2021-01-26 15:32 ` Ferruh Yigit
2021-01-18 9:36 ` [dpdk-dev] [PATCH v2 10/11] net/octeontx_ep: Receive data path function added Nalla Pradeep
2021-01-26 15:33 ` Ferruh Yigit
2021-01-18 9:36 ` [dpdk-dev] [PATCH v2 11/11] net/octeontx_ep: Transmit " Nalla Pradeep
2021-01-26 15:35 ` Ferruh Yigit
2021-01-19 11:50 ` [dpdk-dev] [PATCH v2 01/11] net/octeontx_ep: add build and doc infrastructure Jerin Jacob
2021-01-26 15:09 ` Ferruh Yigit
2021-01-26 15:41 ` Ferruh Yigit
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 00/11] Octeon Tx/Tx2 Endpoint pmd Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 00/12] " Nalla Pradeep
2021-01-29 12:44 ` [dpdk-dev] [PATCH v7 " Nalla Pradeep
2021-01-29 14:08 ` Ferruh Yigit
2021-01-29 12:44 ` [dpdk-dev] [PATCH v7 01/12] raw/octeontx_ep: changed device id Nalla Pradeep
2021-02-11 0:58 ` Radha Mohan
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 02/12] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 03/12] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 04/12] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-29 12:45 ` Nalla Pradeep [this message]
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 06/12] net/octeontx_ep: add dev info get and configure Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 07/12] net/octeontx_ep: added rxq setup and release Nalla Pradeep
2021-01-29 14:04 ` Ferruh Yigit
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 08/12] net/octeontx_ep: added tx queue " Nalla Pradeep
2021-01-29 14:04 ` Ferruh Yigit
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 09/12] net/octeontx_ep: setting up iq and oq registers Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 10/12] net/octeontx_ep: added dev start and stop Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 11/12] net/octeontx_ep: receive data path function added Nalla Pradeep
2021-01-29 12:45 ` [dpdk-dev] [PATCH v7 12/12] net/octeontx_ep: transmit " Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 01/12] raw/octeontx_ep: changed device id Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 02/12] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 03/12] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 04/12] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-29 9:19 ` Ferruh Yigit
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 05/12] net/octeontx_ep: added basic device setup Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 06/12] net/octeontx_ep: add dev info get and configure Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 07/12] net/octeontx_ep: added rxq setup and release Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 08/12] net/octeontx_ep: added tx queue " Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 09/12] net/octeontx_ep: setting up iq and oq registers Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 10/12] net/octeontx_ep: added dev start and stop Nalla Pradeep
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 11/12] net/octeontx_ep: receive data path function added Nalla Pradeep
2021-01-29 9:24 ` Ferruh Yigit
2021-01-29 0:16 ` [dpdk-dev] [PATCH v6 12/12] net/octeontx_ep: transmit " Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 01/11] net/octeontx_ep: add build and doc infrastructure Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 02/11] net/octeontx_ep: add ethdev probe and remove Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 03/11] net/octeontx_ep: add device init and uninit Nalla Pradeep
2021-01-28 16:55 ` Ferruh Yigit
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 04/11] net/octeontx_ep: added basic device setup Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 05/11] net/octeontx_ep: add dev info get and configure Nalla Pradeep
2021-01-28 16:56 ` Ferruh Yigit
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 06/11] net/octeontx_ep: added rxq setup and release Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 07/11] net/octeontx_ep: added tx queue " Nalla Pradeep
2021-01-28 16:57 ` Ferruh Yigit
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 08/11] net/octeontx_ep: setting up iq and oq registers Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 09/11] net/octeontx_ep: added dev start and stop Nalla Pradeep
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 10/11] net/octeontx_ep: receive data path function added Nalla Pradeep
2021-01-28 16:58 ` Ferruh Yigit
2021-01-28 15:22 ` [dpdk-dev] [PATCH v5 11/11] net/octeontx_ep: transmit " Nalla Pradeep
2021-01-28 16:59 ` Ferruh Yigit
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