From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E6AAA09E4; Fri, 29 Jan 2021 13:45:51 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA7B32401F2; Fri, 29 Jan 2021 13:45:24 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C71B02401E4 for ; Fri, 29 Jan 2021 13:45:17 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10TCZ3Pv023534 for ; Fri, 29 Jan 2021 04:45:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=iP2ziV6YDJUeSmxFAk/NMcDL4EFSPKn/XMelBGXDMSw=; b=Ats0Y95v31dZVaE2qhTXtiT883rY+kI/C34x3v3cRwhvVA2XlxbRKxwOHhDsTSO6AGS0 Xm8aeTGuWgZ1OV2KSTele0W7k5RNt6EqylxbHkTk/k409EfqE7pErMtHmrMNF0S+2Qmg J89ywxSLmSQTRpYBWCY8sF+j3G/Cn93wYxpLWmO7HxzUOjRk6aEpgnSU/5aKh65fZgJk FSZkd47QG79ZJ/F33IZk+85ZGqhe6w7rcQIV7mMHKwUGWycIFS6hLZC84XYZLy6xxpeW 7m6BFf5UkriSSIB8ejvZsCI6095mb2zDDhU7hRP2Gc8kgrov1Ek9OnY1IBJKsAKlGQz5 bA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 36b1xpqw4v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 29 Jan 2021 04:45:16 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 Jan 2021 04:45:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 Jan 2021 04:45:14 -0800 Received: from sburla-PowerEdge-T630.caveonetworks.com (unknown [10.106.27.217]) by maili.marvell.com (Postfix) with ESMTP id AA2E13F7044; Fri, 29 Jan 2021 04:45:14 -0800 (PST) From: Nalla Pradeep To: Nalla Pradeep , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Fri, 29 Jan 2021 04:45:04 -0800 Message-ID: <20210129124510.12158-7-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210129001640.1251-1-pnalla@marvell.com> References: <20210129001640.1251-1-pnalla@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-01-29_05:2021-01-28, 2021-01-29 signatures=0 Subject: [dpdk-dev] [PATCH v7 06/12] net/octeontx_ep: add dev info get and configure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add device information get and device configure operations. Signed-off-by: Nalla Pradeep --- doc/guides/nics/features/octeontx_ep.ini | 1 + drivers/net/octeontx_ep/otx_ep_common.h | 14 ++++ drivers/net/octeontx_ep/otx_ep_ethdev.c | 81 +++++++++++++++++++++++- drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 +++ 4 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h diff --git a/doc/guides/nics/features/octeontx_ep.ini b/doc/guides/nics/features/octeontx_ep.ini index 660fbc287..d1453f5be 100644 --- a/doc/guides/nics/features/octeontx_ep.ini +++ b/doc/guides/nics/features/octeontx_ep.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = P SR-IOV = Y Linux = Y x86-64 = Y diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index c138c2dc7..4588a2936 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -7,9 +7,12 @@ #define OTX_EP_MAX_RINGS_PER_VF (8) #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF #define OTX_EP_64BYTE_INSTR (64) +#define OTX_EP_MIN_IQ_DESCRIPTORS (128) +#define OTX_EP_MIN_OQ_DESCRIPTORS (128) #define OTX_EP_MAX_IQ_DESCRIPTORS (8192) #define OTX_EP_MAX_OQ_DESCRIPTORS (8192) #define OTX_EP_OQ_BUF_SIZE (2048) +#define OTX_EP_MIN_RX_BUF_SIZE (64) #define OTX_EP_OQ_INFOPTR_MODE (0) #define OTX_EP_OQ_REFIL_THRESHOLD (16) @@ -115,12 +118,23 @@ struct otx_ep_device { struct otx_ep_fn_list fn_list; + uint32_t max_tx_queues; + + uint32_t max_rx_queues; + /* SR-IOV info */ struct otx_ep_sriov_info sriov_info; /* Device configuration */ const struct otx_ep_config *conf; + + uint64_t rx_offloads; + + uint64_t tx_offloads; }; +#define OTX_EP_MAX_PKT_SZ 64000U +#define OTX_EP_MAX_MAC_ADDRS 1 + extern int otx_net_ep_logtype; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index feb1335dd..a8a1fb867 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -8,8 +8,49 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" #include "otx2_ep_vf.h" +#include "otx_ep_rxtx.h" + +#define OTX_EP_DEV(_eth_dev) \ + ((struct otx_ep_device *)(_eth_dev)->data->dev_private) + +static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = { + .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS, + .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS, + .nb_align = OTX_EP_RXD_ALIGN, +}; + +static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = { + .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS, + .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS, + .nb_align = OTX_EP_TXD_ALIGN, +}; + +static int +otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *devinfo) +{ + struct otx_ep_device *otx_epvf; + + otx_epvf = OTX_EP_DEV(eth_dev); + + devinfo->speed_capa = ETH_LINK_SPEED_10G; + devinfo->max_rx_queues = otx_epvf->max_rx_queues; + devinfo->max_tx_queues = otx_epvf->max_tx_queues; + + devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE; + devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ; + devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME; + devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER; + devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS; + + devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS; + + devinfo->rx_desc_lim = otx_ep_rx_desc_lim; + devinfo->tx_desc_lim = otx_ep_tx_desc_lim; + + return 0; +} -#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) static int otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) { @@ -42,6 +83,7 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) static int otx_epdev_init(struct otx_ep_device *otx_epvf) { + uint32_t ethdev_queues; int ret = 0; ret = otx_ep_chip_specific_setup(otx_epvf); @@ -52,12 +94,48 @@ otx_epdev_init(struct otx_ep_device *otx_epvf) otx_epvf->fn_list.setup_device_regs(otx_epvf); + ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf); + otx_epvf->max_rx_queues = ethdev_queues; + otx_epvf->max_tx_queues = ethdev_queues; + otx_ep_info("OTX_EP Device is Ready\n"); setup_fail: return ret; } +static int +otx_ep_dev_configure(struct rte_eth_dev *eth_dev) +{ + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + struct rte_eth_dev_data *data = eth_dev->data; + struct rte_eth_rxmode *rxmode; + struct rte_eth_txmode *txmode; + struct rte_eth_conf *conf; + + conf = &data->dev_conf; + rxmode = &conf->rxmode; + txmode = &conf->txmode; + if (eth_dev->data->nb_rx_queues > otx_epvf->max_rx_queues || + eth_dev->data->nb_tx_queues > otx_epvf->max_tx_queues) { + otx_ep_err("invalid num queues\n"); + return -EINVAL; + } + otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n", + eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues); + + otx_epvf->rx_offloads = rxmode->offloads; + otx_epvf->tx_offloads = txmode->offloads; + + return 0; +} + +/* Define our ethernet definitions */ +static const struct eth_dev_ops otx_ep_eth_dev_ops = { + .dev_configure = otx_ep_dev_configure, + .dev_infos_get = otx_ep_dev_info_get, +}; + static int otx_ep_eth_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev) { @@ -77,6 +155,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) otx_epvf->eth_dev = eth_dev; otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->dev_ops = &otx_ep_eth_dev_ops; eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); if (eth_dev->data->mac_addrs == NULL) { otx_ep_err("MAC addresses memory allocation failed\n"); diff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.h b/drivers/net/octeontx_ep/otx_ep_rxtx.h new file mode 100644 index 000000000..9779e96b6 --- /dev/null +++ b/drivers/net/octeontx_ep/otx_ep_rxtx.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _OTX_EP_RXTX_H_ +#define _OTX_EP_RXTX_H_ + +#define OTX_EP_RXD_ALIGN 1 +#define OTX_EP_TXD_ALIGN 1 +#endif -- 2.17.1