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From: Yuying Zhang <yuying.zhang@intel.com>
To: dev@dpdk.org, qi.z.zhang@intel.com, haiyue.wang@intel.com
Cc: qi.fu@intel.com, Yuying Zhang <yuying.zhang@intel.com>
Subject: [dpdk-dev] [PATCH v1] net/ice: fix QinQ switch rule input set mask
Date: Thu,  4 Feb 2021 06:07:51 +0000	[thread overview]
Message-ID: <20210204060751.515216-1-yuying.zhang@intel.com> (raw)

QinQ switch rule doesn't support ethertype field match.
QinQ ethertype pattern should not be created. Change the
input set mask to fix the issue.

Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch")

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
---
 drivers/net/ice/ice_switch_filter.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c
index 5ca0985e21..6525e6c115 100644
--- a/drivers/net/ice/ice_switch_filter.c
+++ b/drivers/net/ice/ice_switch_filter.c
@@ -38,7 +38,8 @@
 	ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \
 	ICE_INSET_VLAN_INNER)
 #define ICE_SW_INSET_MAC_QINQ  ( \
-	ICE_SW_INSET_MAC_VLAN | ICE_INSET_VLAN_OUTER)
+	ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_VLAN_INNER | \
+	ICE_INSET_VLAN_OUTER)
 #define ICE_SW_INSET_MAC_IPV4 ( \
 	ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
 	ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)
-- 
2.25.1


             reply	other threads:[~2021-02-04  6:15 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04  6:07 Yuying Zhang [this message]
2021-02-04  8:06 ` Zhang, Qi Z

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