From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F614A09E4; Fri, 5 Feb 2021 04:34:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 307B51606D5; Fri, 5 Feb 2021 04:34:42 +0100 (CET) Received: from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102]) by mails.dpdk.org (Postfix) with ESMTP id 47ABF1606D5 for ; Fri, 5 Feb 2021 04:34:40 +0100 (CET) X-QQ-mid: bizesmtp27t1612496075tqv4oj5k Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Fri, 05 Feb 2021 11:34:35 +0800 (CST) X-QQ-SSF: 01400000002000C0D000B00A0000000 X-QQ-FEAT: YKCDl5A3/arc2JyhJfQdG52Paui+mKsJimKm0kG2sZEGLPj5O7mlyGJknHIfN fiE8L65FiQRYEgMCzcyHn46uVl6VT4Hme/UrkeewJnpfQDe00WO+YyLKTi3/3xlzTLuBAOT TsLebHFrURdPSm83n9aKeVviTRNx5RQQJWyThittj6kkibp3kz+PzONU9CTvKmGjxiQIpRz bwL6OHRPdDag/XHqdNNjNP/CHp0VlwZRnkqLFLeubujPt6S29e2tbdGesX0yaiu4kc/V1cz JxMs94rrmMNh4PXy6p4O0fTbN9VZwiV/qoagN0EWIelPGAhAvhmVUQZHYjOMRdtfZUDPeuH SDRtjPq8CrF5b8fxkPQiM77CUqN8g== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Fri, 5 Feb 2021 11:34:36 +0800 Message-Id: <20210205033449.3813939-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210205033449.3813939-1-jiawenwu@trustnetic.com> References: <20210205033449.3813939-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign6 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v2 04/17] net/txgbe: get VF device information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add information get operation for VF device. RX and TX offload capabilities are same as the PF device. Signed-off-by: Jiawen Wu --- doc/guides/nics/features/txgbe_vf.ini | 7 +++ drivers/net/txgbe/txgbe_ethdev_vf.c | 70 +++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/doc/guides/nics/features/txgbe_vf.ini b/doc/guides/nics/features/txgbe_vf.ini index 5035c5eea..777ba9183 100644 --- a/doc/guides/nics/features/txgbe_vf.ini +++ b/doc/guides/nics/features/txgbe_vf.ini @@ -4,6 +4,13 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +CRC offload = P +VLAN offload = P +QinQ offload = P +L3 checksum offload = P +L4 checksum offload = P +Inner L3 checksum = P +Inner L4 checksum = P Multiprocess aware = Y Linux = Y ARMv8 = Y diff --git a/drivers/net/txgbe/txgbe_ethdev_vf.c b/drivers/net/txgbe/txgbe_ethdev_vf.c index f9b30b116..1db944c7b 100644 --- a/drivers/net/txgbe/txgbe_ethdev_vf.c +++ b/drivers/net/txgbe/txgbe_ethdev_vf.c @@ -15,6 +15,8 @@ #include "txgbe_ethdev.h" #include "txgbe_rxtx.h" +static int txgbevf_dev_info_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); static int txgbevf_dev_close(struct rte_eth_dev *dev); static void txgbevf_intr_disable(struct rte_eth_dev *dev); static void txgbevf_intr_enable(struct rte_eth_dev *dev); @@ -29,6 +31,20 @@ static const struct rte_pci_id pci_id_txgbevf_map[] = { { .vendor_id = 0, /* sentinel */ }, }; +static const struct rte_eth_desc_lim rx_desc_lim = { + .nb_max = TXGBE_RING_DESC_MAX, + .nb_min = TXGBE_RING_DESC_MIN, + .nb_align = TXGBE_RXD_ALIGN, +}; + +static const struct rte_eth_desc_lim tx_desc_lim = { + .nb_max = TXGBE_RING_DESC_MAX, + .nb_min = TXGBE_RING_DESC_MIN, + .nb_align = TXGBE_TXD_ALIGN, + .nb_seg_max = TXGBE_TX_MAX_SEG, + .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, +}; + static const struct eth_dev_ops txgbevf_eth_dev_ops; /* @@ -246,6 +262,57 @@ static struct rte_pci_driver rte_txgbevf_pmd = { .remove = eth_txgbevf_pci_remove, }; +static int +txgbevf_dev_info_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + + dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; + dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; + dev_info->min_rx_bufsize = 1024; + dev_info->max_rx_pktlen = TXGBE_FRAME_SIZE_MAX; + dev_info->max_mac_addrs = hw->mac.num_rar_entries; + dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; + dev_info->max_vfs = pci_dev->max_vfs; + dev_info->max_vmdq_pools = ETH_64_POOLS; + dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); + dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | + dev_info->rx_queue_offload_capa); + dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); + dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); + dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); + dev_info->reta_size = ETH_RSS_RETA_SIZE_128; + dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_thresh = { + .pthresh = TXGBE_DEFAULT_RX_PTHRESH, + .hthresh = TXGBE_DEFAULT_RX_HTHRESH, + .wthresh = TXGBE_DEFAULT_RX_WTHRESH, + }, + .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, + .rx_drop_en = 0, + .offloads = 0, + }; + + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_thresh = { + .pthresh = TXGBE_DEFAULT_TX_PTHRESH, + .hthresh = TXGBE_DEFAULT_TX_HTHRESH, + .wthresh = TXGBE_DEFAULT_TX_WTHRESH, + }, + .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, + .offloads = 0, + }; + + dev_info->rx_desc_lim = rx_desc_lim; + dev_info->tx_desc_lim = tx_desc_lim; + + return 0; +} + /* * Virtual Function operations */ @@ -408,8 +475,11 @@ txgbevf_set_default_mac_addr(struct rte_eth_dev *dev, * operation have been implemented */ static const struct eth_dev_ops txgbevf_eth_dev_ops = { + .dev_infos_get = txgbevf_dev_info_get, .mac_addr_add = txgbevf_add_mac_addr, .mac_addr_remove = txgbevf_remove_mac_addr, + .rxq_info_get = txgbe_rxq_info_get, + .txq_info_get = txgbe_txq_info_get, .mac_addr_set = txgbevf_set_default_mac_addr, }; -- 2.27.0