From: Qi Zhang <qi.z.zhang@intel.com>
To: qiming.yang@intel.com
Cc: dev@dpdk.org, haiyue.wang@intel.com, junfeng.guo@intel.com,
Qi Zhang <qi.z.zhang@intel.com>, Amir Shay <shay.amir@intel.com>
Subject: [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction
Date: Tue, 2 Mar 2021 15:23:46 +0800 [thread overview]
Message-ID: <20210302072357.1657556-4-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20210302072357.1657556-1-qi.z.zhang@intel.com>
Add capability which indicates double reset solution restriction.
Added "Post-update EMPR enabled" field to "Response Flags" field
(byte 19 in the response structure).
Signed-off-by: Amir Shay <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 3f2b4cd54b..a31c27a633 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -111,6 +111,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_MAX_MTU 0x0047
#define ICE_AQC_CAPS_IWARP 0x0051
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
+#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define ICE_AQC_CAPS_NVM_MGMT 0x0080
u8 major_ver;
@@ -1765,6 +1766,7 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
#define ICE_AQC_NVM_PERST_FLAG 1
#define ICE_AQC_NVM_EMPR_FLAG 2
+#define ICE_AQC_NVM_EMPR_ENA BIT(0)
__le16 module_typeid;
__le16 length;
#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
--
2.26.2
next prev parent reply other threads:[~2021-03-02 7:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-02 7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming Qi Zhang
2021-03-02 7:23 ` Qi Zhang [this message]
2021-03-02 7:23 ` [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow) Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues Qi Zhang
2021-03-04 5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
2021-03-05 8:39 ` Zhang, Qi Z
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