From: Qi Zhang <qi.z.zhang@intel.com>
To: qiming.yang@intel.com
Cc: dev@dpdk.org, haiyue.wang@intel.com, junfeng.guo@intel.com,
Qi Zhang <qi.z.zhang@intel.com>
Subject: [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR
Date: Tue, 2 Mar 2021 15:23:51 +0800 [thread overview]
Message-ID: <20210302072357.1657556-9-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20210302072357.1657556-1-qi.z.zhang@intel.com>
Support IPV4_GTPU with inner IPV6/UDP/TCP for FDIR.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 106 ++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_fdir.h | 9 +++
drivers/net/ice/base/ice_type.h | 3 +
3 files changed, 118 insertions(+)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 3df3de1bdb..689e96da1e 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -249,6 +249,54 @@ static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {
0x00, 0x00,
};
+static const u8 ice_fdir_ipv6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
+ 0x24, 0x42, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x54, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x40,
+ 0x4e, 0x3d, 0x30, 0xff, 0x00, 0x30, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0xff, 0xdc, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,
+ 0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_ipv6_gtpu6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
@@ -802,6 +850,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_ipv4_gtpu4_pkt),
ice_fdir_ipv4_gtpu4_pkt,
},
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_pkt),
+ ice_fdir_ipv6_gtpu4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_pkt),
+ ice_fdir_ipv6_gtpu4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_pkt),
+ ice_fdir_udp6_gtpu4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_pkt),
+ ice_fdir_udp6_gtpu4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_pkt),
+ ice_fdir_tcp6_gtpu4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_pkt),
+ ice_fdir_tcp6_gtpu4_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
sizeof(ice_fdir_ipv6_gtpu6_pkt),
@@ -1391,6 +1460,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:
ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
ice_fdir_pkt[idx].tun_pkt_len,
ICE_NONDMA_TO_NONDMA);
@@ -1575,6 +1647,40 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);
ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+ ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+ ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_PROTO_OFFSET,
+ input->ip.v6.proto);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v6.src_port);
+ ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v6.dst_port);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+ ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v6.src_port);
+ ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v6.dst_port);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+ ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+ break;
case ICE_FLTR_PTYPE_NONF_IPV6_GTPU:
case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index e236f13f05..6573f96bc1 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -56,6 +56,15 @@
#define ICE_TCP4_NO_MAC_DST_PORT_OFFSET 22
#define ICE_UDP4_NO_MAC_SRC_PORT_OFFSET 20
#define ICE_UDP4_NO_MAC_DST_PORT_OFFSET 22
+#define ICE_IPV6_NO_MAC_TC_OFFSET 0
+#define ICE_IPV6_NO_MAC_HLIM_OFFSET 7
+#define ICE_IPV6_NO_MAC_PROTO_OFFSET 6
+#define ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET 8
+#define ICE_IPV6_NO_MAC_DST_ADDR_OFFSET 24
+#define ICE_TCP6_NO_MAC_SRC_PORT_OFFSET 40
+#define ICE_TCP6_NO_MAC_DST_PORT_OFFSET 42
+#define ICE_UDP6_NO_MAC_SRC_PORT_OFFSET 40
+#define ICE_UDP6_NO_MAC_DST_PORT_OFFSET 42
#define ICE_IPV4_GTPU_TEID_OFFSET 46
#define ICE_IPV4_GTPU_QFI_OFFSET 56
#define ICE_IPV6_GTPU_TEID_OFFSET 66
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 102c209286..2550e0e19f 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -316,6 +316,9 @@ enum ice_fltr_ptype {
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
--
2.26.2
next prev parent reply other threads:[~2021-03-02 7:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-02 7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow) Qi Zhang
2021-03-02 7:23 ` Qi Zhang [this message]
2021-03-02 7:23 ` [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct Qi Zhang
2021-03-02 7:23 ` [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues Qi Zhang
2021-03-04 5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
2021-03-05 8:39 ` Zhang, Qi Z
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