From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AFF6EA0547; Fri, 5 Mar 2021 14:44:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A299822A3E5; Fri, 5 Mar 2021 14:40:49 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3195222A378 for ; Fri, 5 Mar 2021 14:40:48 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 125DelHS001661 for ; Fri, 5 Mar 2021 05:40:47 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=SxWAg75HfvPOmnQ3PHI1TnaWv7TPa6jz9hBD2M7/LqA=; b=AHPEoc6Tb9pzhrkfg2Z3BPOeuUgDt6ELFyj4XD3nKG9FrcP4m4pxrDaXPwacwXOer71b fTPuZ89ouG8czp9fxt6UddJiZ4LzLFaRviuJ7dAEk2pNgzmrclHOBZFuaiMMS6YE9SYQ eWzsHm1LZaHJ9UxDqq3wPiHY+1L2dQ+IVgjnAU0KCB5TVE1SMYO8eCWUNuuBR3HGrcC1 Css6afaLLA3p94B+Mdxm9DWQowTVJ+Bfp+05TMEwR4qy7gyvShng/3boi6ka7U7YLUm8 /ctJiMLphyvG702wBjIP/szsKw7UtXrkNPd3D5ZUEVjEob0/0JE+QF57pDoW8e+joxZK vA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrp7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 05 Mar 2021 05:40:47 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 5 Mar 2021 05:40:41 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 5 Mar 2021 05:40:40 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 5 Mar 2021 05:40:40 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 87D363F7044; Fri, 5 Mar 2021 05:40:38 -0800 (PST) From: Nithin Dabilpuram To: CC: , , , , , , Date: Fri, 5 Mar 2021 19:08:50 +0530 Message-ID: <20210305133918.8005-25-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210305133918.8005-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-05_08:2021-03-03, 2021-03-05 signatures=0 Subject: [dpdk-dev] [PATCH 24/52] common/cnxk: add nix RSS support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add API's for default/non-default reta table setup, key set/get, and flow algo setup for CN9K and CN10K. Signed-off-by: Jerin Jacob --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_nix.h | 17 +++ drivers/common/cnxk/roc_nix_rss.c | 219 ++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 7 ++ 4 files changed, 244 insertions(+) create mode 100644 drivers/common/cnxk/roc_nix_rss.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index bde5728..36c3ada 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -22,6 +22,7 @@ sources = files('roc_dev.c', 'roc_nix_mcast.c', 'roc_nix_npc.c', 'roc_nix_queue.c', + 'roc_nix_rss.c', 'roc_npa.c', 'roc_npa_debug.c', 'roc_npa_irq.c', diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 34057b9..0409040 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -215,6 +215,23 @@ int __roc_api roc_nix_npc_rx_ena_dis(struct roc_nix *roc_nix, bool enable); int __roc_api roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool mcast_enable, bool prom_enable); +/* RSS */ +void __roc_api roc_nix_rss_key_default_fill(struct roc_nix *roc_nix, + uint8_t key[ROC_NIX_RSS_KEY_LEN]); +void __roc_api roc_nix_rss_key_set(struct roc_nix *roc_nix, + uint8_t key[ROC_NIX_RSS_KEY_LEN]); +void __roc_api roc_nix_rss_key_get(struct roc_nix *roc_nix, + uint8_t key[ROC_NIX_RSS_KEY_LEN]); +int __roc_api roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]); +int __roc_api roc_nix_rss_reta_get(struct roc_nix *roc_nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]); +int __roc_api roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx, + uint32_t flowkey, uint8_t group, + int mcam_index); +int __roc_api roc_nix_rss_default_setup(struct roc_nix *roc_nix, + uint32_t flowkey); + /* Queue */ int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena); diff --git a/drivers/common/cnxk/roc_nix_rss.c b/drivers/common/cnxk/roc_nix_rss.c new file mode 100644 index 0000000..add411e --- /dev/null +++ b/drivers/common/cnxk/roc_nix_rss.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2020 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +void +roc_nix_rss_key_default_fill(struct roc_nix *roc_nix, + uint8_t key[ROC_NIX_RSS_KEY_LEN]) +{ + PLT_SET_USED(roc_nix); + const uint8_t default_key[ROC_NIX_RSS_KEY_LEN] = { + 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, + 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, + 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, + 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, + 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD}; + + memcpy(key, default_key, ROC_NIX_RSS_KEY_LEN); +} + +void +roc_nix_rss_key_set(struct roc_nix *roc_nix, uint8_t key[ROC_NIX_RSS_KEY_LEN]) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint64_t *keyptr; + uint64_t val; + uint32_t idx; + + keyptr = (uint64_t *)key; + for (idx = 0; idx < (ROC_NIX_RSS_KEY_LEN >> 3); idx++) { + val = plt_cpu_to_be_64(keyptr[idx]); + plt_write64(val, nix->base + NIX_LF_RX_SECRETX(idx)); + } +} + +void +roc_nix_rss_key_get(struct roc_nix *roc_nix, uint8_t key[ROC_NIX_RSS_KEY_LEN]) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint64_t *keyptr = (uint64_t *)key; + uint64_t val; + uint32_t idx; + + for (idx = 0; idx < (ROC_NIX_RSS_KEY_LEN >> 3); idx++) { + val = plt_read64(nix->base + NIX_LF_RX_SECRETX(idx)); + keyptr[idx] = plt_be_to_cpu_64(val); + } +} + +static int +nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]) +{ + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_aq_enq_req *req; + uint16_t idx; + int rc; + + for (idx = 0; idx < nix->reta_sz; idx++) { + req = mbox_alloc_msg_nix_aq_enq(mbox); + if (!req) { + /* The shared memory buffer can be full. + * Flush it and retry + */ + rc = mbox_process(mbox); + if (rc < 0) + return rc; + req = mbox_alloc_msg_nix_aq_enq(mbox); + if (!req) + return NIX_ERR_NO_MEM; + } + req->rss.rq = reta[idx]; + /* Fill AQ info */ + req->qidx = (group * nix->reta_sz) + idx; + req->ctype = NIX_AQ_CTYPE_RSS; + req->op = NIX_AQ_INSTOP_INIT; + } + + rc = mbox_process(mbox); + if (rc < 0) + return rc; + + return 0; +} + +static int +nix_rss_reta_set(struct nix *nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]) +{ + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_cn10k_aq_enq_req *req; + uint16_t idx; + int rc; + + for (idx = 0; idx < nix->reta_sz; idx++) { + req = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (!req) { + /* The shared memory buffer can be full. + * Flush it and retry + */ + rc = mbox_process(mbox); + if (rc < 0) + return rc; + req = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (!req) + return NIX_ERR_NO_MEM; + } + req->rss.rq = reta[idx]; + /* Fill AQ info */ + req->qidx = (group * nix->reta_sz) + idx; + req->ctype = NIX_AQ_CTYPE_RSS; + req->op = NIX_AQ_INSTOP_INIT; + } + + rc = mbox_process(mbox); + if (rc < 0) + return rc; + + return 0; +} + +int +roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int rc; + + if (group >= ROC_NIX_RSS_GRPS) + return NIX_ERR_PARAM; + + if (roc_model_is_cn9k()) + rc = nix_cn9k_rss_reta_set(nix, group, reta); + else + rc = nix_rss_reta_set(nix, group, reta); + if (rc) + return rc; + + memcpy(&nix->reta[group], reta, ROC_NIX_RSS_RETA_MAX); + return 0; +} + +int +roc_nix_rss_reta_get(struct roc_nix *roc_nix, uint8_t group, + uint16_t reta[ROC_NIX_RSS_RETA_MAX]) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + if (group >= ROC_NIX_RSS_GRPS) + return NIX_ERR_PARAM; + + memcpy(reta, &nix->reta[group], ROC_NIX_RSS_RETA_MAX); + return 0; +} + +int +roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx, + uint32_t flowkey, uint8_t group, int mcam_index) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_rss_flowkey_cfg_rsp *rss_rsp; + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_rss_flowkey_cfg *cfg; + int rc = -ENOSPC; + + if (group >= ROC_NIX_RSS_GRPS) + return NIX_ERR_PARAM; + + cfg = mbox_alloc_msg_nix_rss_flowkey_cfg(mbox); + if (cfg == NULL) + return rc; + cfg->flowkey_cfg = flowkey; + cfg->mcam_index = mcam_index; /* -1 indicates default group */ + cfg->group = group; /* 0 is default group */ + rc = mbox_process_msg(mbox, (void *)&rss_rsp); + if (rc) + return rc; + if (alg_idx) + *alg_idx = rss_rsp->alg_idx; + + return rc; +} + +int +roc_nix_rss_default_setup(struct roc_nix *roc_nix, uint32_t flowkey) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint16_t idx, qcnt = nix->nb_rx_queues; + uint16_t reta[ROC_NIX_RSS_RETA_MAX]; + uint8_t key[ROC_NIX_RSS_KEY_LEN]; + uint8_t alg_idx; + int rc; + + roc_nix_rss_key_default_fill(roc_nix, key); + roc_nix_rss_key_set(roc_nix, key); + + /* Update default RSS RETA */ + for (idx = 0; idx < nix->reta_sz; idx++) + reta[idx] = idx % qcnt; + rc = roc_nix_rss_reta_set(roc_nix, 0, reta); + if (rc) { + plt_err("Failed to set RSS reta table rc=%d", rc); + goto fail; + } + + /* Update the default flowkey */ + rc = roc_nix_rss_flowkey_set(roc_nix, &alg_idx, flowkey, + ROC_NIX_RSS_GROUP_DEFAULT, -1); + if (rc) { + plt_err("Failed to set RSS flowkey rc=%d", rc); + goto fail; + } + + nix->rss_alg_idx = alg_idx; +fail: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 53ed0e1..f8f6b89 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -63,6 +63,13 @@ INTERNAL { roc_nix_rq_fini; roc_nix_rq_init; roc_nix_rq_modify; + roc_nix_rss_default_setup; + roc_nix_rss_flowkey_set; + roc_nix_rss_key_default_fill; + roc_nix_rss_key_get; + roc_nix_rss_key_set; + roc_nix_rss_reta_get; + roc_nix_rss_reta_set; roc_nix_rx_queue_intr_disable; roc_nix_rx_queue_intr_enable; roc_nix_sq_fini; -- 2.8.4