From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61721A0548; Sat, 6 Mar 2021 16:38:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 12CB922A421; Sat, 6 Mar 2021 16:35:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3586D22A421 for ; Sat, 6 Mar 2021 16:35:36 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126FWlRW029538 for ; Sat, 6 Mar 2021 07:35:35 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=tFdpnjZCnEQOOifRO/LCQBL50Y5D805l9EI4vlw+jG0=; b=cO3V4YCN7S9V/kgiXQbr+4BMK/uw/Yoh9rr0ocbrodYSJdYsCwXDP4+ojbF1L7NgySLz TkrbLleGTzzeELLt1an9kMJFD34nbYBuIvD54XttiPbGmN9BoK7zf3g/qmdyvk50d9fU qus7+cnRwxqCbISee93TkMbhF4LToaOXxVP7IJxpN3VQjaMK/vz76pw5e7tl9LHl1phT 5zcZbV6B9qKQh4tmVgvN2oWkbuvMFcvPZwrqXkrUELW/NT0m34IQ/htxlQTqJn3BAiRJ YBmq01a54zyDr4selERRYDoU7nNRPjsEmwRs2CmRURb1tkFD/VLtbPtpifLU/3IEx1gE 0A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3747yurcd0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 06 Mar 2021 07:35:35 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 07:35:33 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 07:35:33 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 738953F703F; Sat, 6 Mar 2021 07:35:31 -0800 (PST) From: Nithin Dabilpuram To: CC: , , , , , , Date: Sat, 6 Mar 2021 21:03:45 +0530 Message-ID: <20210306153404.10781-26-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210306153404.10781-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 25/44] net/cnxk: add MTU set device operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori This Patch implements mtu set dev op for cn9k and cn10k platforms. Signed-off-by: Sunil Kumar Kori --- doc/guides/nics/cnxk.rst | 1 + doc/guides/nics/features/cnxk.ini | 1 + doc/guides/nics/features/cnxk_vec.ini | 1 + doc/guides/nics/features/cnxk_vf.ini | 1 + drivers/net/cnxk/cnxk_ethdev.c | 51 +++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.h | 5 ++- drivers/net/cnxk/cnxk_ethdev_ops.c | 77 ++++++++++++++++++++++++++++++++++- 7 files changed, 135 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 42aa7a5..6cb90a7 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -24,6 +24,7 @@ Features of the CNXK Ethdev PMD are: - Receiver Side Scaling (RSS) - Inner and Outer Checksum offload - Link state information +- MTU update - Scatter-Gather IO support - Vector Poll mode driver diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 02be26b..6fef725 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -15,6 +15,7 @@ Runtime Tx queue setup = Y Fast mbuf free = Y Free Tx mbuf on demand = Y Queue start/stop = Y +MTU update = Y TSO = Y RSS hash = Y Inner RSS = Y diff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini index 8c63853..79cb1e2 100644 --- a/doc/guides/nics/features/cnxk_vec.ini +++ b/doc/guides/nics/features/cnxk_vec.ini @@ -15,6 +15,7 @@ Runtime Tx queue setup = Y Fast mbuf free = Y Free Tx mbuf on demand = Y Queue start/stop = Y +MTU update = Y RSS hash = Y Inner RSS = Y Jumbo frame = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index a1bd49b..5cc9f3f 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -14,6 +14,7 @@ Runtime Tx queue setup = Y Fast mbuf free = Y Free Tx mbuf on demand = Y Queue start/stop = Y +MTU update = Y TSO = Y RSS hash = Y Inner RSS = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index ed01087..9040ce6 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -37,6 +37,50 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) return speed_capa; } +static void +nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq) +{ + struct rte_pktmbuf_pool_private *mbp_priv; + struct rte_eth_dev *eth_dev; + struct cnxk_eth_dev *dev; + uint32_t buffsz; + + dev = rxq->dev; + eth_dev = dev->eth_dev; + + /* Get rx buffer size */ + mbp_priv = rte_mempool_get_priv(rxq->qconf.mp); + buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; + + if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) { + dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER; + dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; + } +} + +static int +nix_recalc_mtu(struct rte_eth_dev *eth_dev) +{ + struct rte_eth_dev_data *data = eth_dev->data; + struct cnxk_eth_rxq_sp *rxq; + uint16_t mtu; + int rc; + + rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1; + /* Setup scatter mode if needed by jumbo */ + nix_enable_mseg_on_jumbo(rxq); + + /* Setup MTU based on max_rx_pkt_len */ + mtu = data->dev_conf.rxmode.max_rx_pkt_len - CNXK_NIX_L2_OVERHEAD + + CNXK_NIX_MAX_VTAG_ACT_SIZE; + + rc = cnxk_nix_mtu_set(eth_dev, mtu); + if (rc) + plt_err("Failed to set default MTU size, rc=%d", rc); + + return rc; +} + uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev) { @@ -955,6 +999,12 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); int rc, i; + if (eth_dev->data->nb_rx_queues != 0) { + rc = nix_recalc_mtu(eth_dev); + if (rc) + return rc; + } + /* Start rx queues */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rc = cnxk_nix_rx_queue_start(eth_dev, i); @@ -999,6 +1049,7 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) /* CNXK platform independent eth dev ops */ struct eth_dev_ops cnxk_eth_dev_ops = { + .mtu_set = cnxk_nix_mtu_set, .mac_addr_set = cnxk_nix_mac_addr_set, .dev_infos_get = cnxk_nix_info_get, .link_update = cnxk_nix_link_update, diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 717a8d8..3838573 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -28,7 +28,9 @@ #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS) /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ -#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8) +#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \ + RTE_ETHER_CRC_LEN + \ + CNXK_NIX_MAX_VTAG_ACT_SIZE) #define CNXK_NIX_RX_MIN_DESC 16 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16 @@ -203,6 +205,7 @@ extern struct eth_dev_ops cnxk_eth_dev_ops; int cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev); int cnxk_nix_remove(struct rte_pci_device *pci_dev); +int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu); int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr); int cnxk_nix_info_get(struct rte_eth_dev *eth_dev, diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 87cf4ee..21b55c4 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -20,7 +20,8 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; devinfo->max_mac_addrs = dev->max_mac_entries; devinfo->max_vfs = pci_dev->max_vfs; - devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD; + devinfo->max_mtu = devinfo->max_rx_pktlen - + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD; devinfo->rx_offload_capa = dev->rx_offload_capa; @@ -98,3 +99,77 @@ cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr) exit: return rc; } + +int +cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) +{ + uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct rte_eth_dev_data *data = eth_dev->data; + struct roc_nix *nix = &dev->nix; + int rc = -EINVAL; + uint32_t buffsz; + + /* Check if MTU is within the allowed range */ + if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) { + plt_err("MTU is lesser than minimum"); + goto exit; + } + + if ((frame_size - RTE_ETHER_CRC_LEN) > + ((uint32_t)roc_nix_max_pkt_len(nix))) { + plt_err("MTU is greater than maximum"); + goto exit; + } + + buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; + old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD; + + /* Refuse MTU that requires the support of scattered packets + * when this feature has not been enabled before. + */ + if (data->dev_started && frame_size > buffsz && + !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)) { + plt_err("Scatter offload is not enabled for mtu"); + goto exit; + } + + /* Check * >= max_frame */ + if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) && + frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) { + plt_err("Greater than maximum supported packet length"); + goto exit; + } + + frame_size -= RTE_ETHER_CRC_LEN; + + /* Update mtu on Tx */ + rc = roc_nix_mac_mtu_set(nix, frame_size); + if (rc) { + plt_err("Failed to set MTU, rc=%d", rc); + goto exit; + } + + /* Sync same frame size on Rx */ + rc = roc_nix_mac_max_rx_len_set(nix, frame_size); + if (rc) { + /* Rollback to older mtu */ + roc_nix_mac_mtu_set(nix, + old_frame_size - RTE_ETHER_CRC_LEN); + plt_err("Failed to max Rx frame length, rc=%d", rc); + goto exit; + } + + frame_size += RTE_ETHER_CRC_LEN; + + if (frame_size > RTE_ETHER_MAX_LEN) + dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; + else + dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; + + /* Update max_rx_pkt_len */ + data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + +exit: + return rc; +} -- 2.8.4