From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C294A0564; Sun, 7 Mar 2021 11:03:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E145A22A38D; Sun, 7 Mar 2021 11:03:05 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 275F322A34E for ; Sun, 7 Mar 2021 11:02:59 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 7 Mar 2021 12:02:55 +0200 Received: from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 127A2qPJ016595; Sun, 7 Mar 2021 12:02:55 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, orika@nvidia.com, thomas@monjalon.net, stable@dpdk.org Date: Sun, 7 Mar 2021 10:02:48 +0000 Message-Id: <20210307100251.22538-3-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210307100251.22538-1-viacheslavo@nvidia.com> References: <20210307100251.22538-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 2/5] net/mlx5: add timestamp format support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.256 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for new added values cause the queue creation reject. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 86fc67fc9315 ("net/mlx5: create advanced RxQ object via DevX") Fixes: ae18a1ae9692 ("net/mlx5: support Tx hairpin queues") Fixes: 15c3807e86ab ("common/mlx5: support DevX QP operations") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 3 +++ drivers/net/mlx5/mlx5.h | 3 +++ drivers/net/mlx5/mlx5_devx.c | 12 +++++++++++- drivers/net/mlx5/mlx5_flow_age.c | 10 ++++++++-- drivers/net/mlx5/mlx5_txpp.c | 8 ++++++++ drivers/net/mlx5/windows/mlx5_os.c | 3 +++ 6 files changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 81eb2e4b05..dca3f92da7 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1162,6 +1162,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->cmng.relaxed_ordering_read = 0; sh->cmng.relaxed_ordering_write = 0; } + sh->rq_ts_format = config->hca_attr.rq_ts_format; + sh->sq_ts_format = config->hca_attr.sq_ts_format; + sh->qp_ts_format = config->hca_attr.qp_ts_format; /* Check for LRO support. */ if (config->dest_tir && config->hca_attr.lro_cap && config->dv_flow_en) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a281fd20ea..058559520e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -681,6 +681,9 @@ struct mlx5_dev_ctx_shared { uint16_t bond_dev; /* Bond primary device id. */ uint32_t devx:1; /* Opened with DV. */ uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ + uint32_t rq_ts_format:2; /* Whether RQ supports timestamp formats. */ + uint32_t sq_ts_format:2; /* Whether SQ supports timestamp formats. */ + uint32_t qp_ts_format:2; /* Whether QP supportstimestamp formats. */ uint32_t max_port; /* Maximal IB device port index. */ void *ctx; /* Verbs/DV/DevX context. */ void *pd; /* Protection Domain. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 2cb3bd1f12..0e74901402 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -440,6 +440,10 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; attr.counter_set_id = priv->counter_set_id; + attr.ts_format = + priv->sh->rq_ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT, tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr, rxq_ctrl->socket); if (!tmpl->rq) { @@ -934,6 +938,9 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; attr.tis_num = priv->sh->tis->id; + /* Check whether timestamp format selection supported in FW. */ + if (priv->sh->sq_ts_format != MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR) + attr.ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr); if (!tmpl->sq) { DRV_LOG(ERR, @@ -996,8 +1003,11 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx, .uar_page = mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar), }, + .ts_format = priv->sh->sq_ts_format == + MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT, }; - /* Create Send Queue object with DevX. */ return mlx5_devx_sq_create(priv->sh->ctx, &txq_obj->sq_obj, log_desc_n, &sq_attr, priv->sh->numa_node); diff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c index 3005afdd33..c8d520b140 100644 --- a/drivers/net/mlx5/mlx5_flow_age.c +++ b/drivers/net/mlx5/mlx5_flow_age.c @@ -202,7 +202,8 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq) */ static int mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, - void *uar, uint32_t pdn, uint16_t log_desc_n) + void *uar, uint32_t pdn, uint16_t log_desc_n, + uint32_t ts_format) { struct mlx5_devx_create_sq_attr attr = { .user_index = 0xFFFF, @@ -210,6 +211,10 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, .pd = pdn, .uar_page = mlx5_os_get_devx_uar_page_id(uar), }, + .ts_format = + ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT, }; struct mlx5_devx_modify_sq_attr modify_attr = { .state = MLX5_SQC_STATE_RDY, @@ -265,7 +270,8 @@ int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh) { return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0, - sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC); + sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC, + sh->sq_ts_format); } /** diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index 696282ca31..ec4d7aaa1b 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -234,6 +234,10 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh) .pd = sh->pdn, .uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar), }, + .ts_format = + sh->sq_ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT, }; struct mlx5_devx_modify_sq_attr msq_attr = { 0 }; struct mlx5_devx_cq_attr cq_attr = { @@ -443,6 +447,10 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh) sq_attr.wq_attr.cd_slave = 1; sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar); sq_attr.wq_attr.pd = sh->pdn; + sq_attr.ts_format = + sh->sq_ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT, ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size), &sq_attr, sh->numa_node); if (ret) { diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index e37cc65c17..d73a0d1502 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -497,6 +497,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, (NS_PER_S / MS_PER_S)) config->rt_timestamp = 1; } + sh->rq_ts_format = config->hca_attr.rq_ts_format; + sh->sq_ts_format = config->hca_attr.sq_ts_format; + sh->qp_ts_format = config->hca_attr.qp_ts_format; } if (config->mprq.enabled) { DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); -- 2.28.0