From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07EDFA0564; Sun, 7 Mar 2021 11:03:36 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EEE7622A3B1; Sun, 7 Mar 2021 11:03:08 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 47DFC22A32F for ; Sun, 7 Mar 2021 11:03:04 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 7 Mar 2021 12:02:58 +0200 Received: from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 127A2qPM016595; Sun, 7 Mar 2021 12:02:57 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, orika@nvidia.com, thomas@monjalon.net, stable@dpdk.org Date: Sun, 7 Mar 2021 10:02:51 +0000 Message-Id: <20210307100251.22538-6-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210307100251.22538-1-viacheslavo@nvidia.com> References: <20210307100251.22538-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 5/5] compress/mlx5: add timestamp format support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add support for the timestamp format settings for the receive and send queues. If the firmware version x.30.256 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for new added values cause the queue creation reject. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/compress/mlx5/mlx5_compress.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 46255ab5e0..97ddfa0c34 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -43,6 +43,7 @@ struct mlx5_compress_priv { void *uar; uint32_t pdn; /* Protection Domain number. */ uint8_t min_block_size; + uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ /* Minimum huffman block size supported by the device. */ struct ibv_pd *pd; struct rte_compressdev_config dev_config; @@ -245,6 +246,9 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, goto err; } sq_attr.cqn = qp->cq.cq->id; + /* Check whether timestamp format selection supported in FW. */ + if (priv->sq_ts_format != MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR) + sq_attr.ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, socket_id); if (ret != 0) { @@ -814,6 +818,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, priv->pci_dev = pci_dev; priv->cdev = cdev; priv->min_block_size = att.compress_min_block_size; + priv->sq_ts_format = att.sq_ts_format; if (mlx5_compress_hw_global_prepare(priv) != 0) { rte_compressdev_pmd_destroy(priv->cdev); claim_zero(mlx5_glue->close_device(priv->ctx)); -- 2.28.0