From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FDFEA0567; Tue, 9 Mar 2021 10:49:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E91C722A4BF; Tue, 9 Mar 2021 10:48:59 +0100 (CET) Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by mails.dpdk.org (Postfix) with ESMTP id A2E7222A4C5 for ; Tue, 9 Mar 2021 10:48:58 +0100 (CET) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id 5753C5C0094; Tue, 9 Mar 2021 04:48:58 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Tue, 09 Mar 2021 04:48:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=qTmPCH+CX6Jgx +qfdfVTpUbaytBSd+JA9aQhJ5aICag=; b=IMdfY3K9B4Sh/Su1NePfBkiEBcZZV AtR587E3zqr5VLP06gqEVuNz+O6/dBUMPQGE6AVRY9fYr+FkYustL1IHgvsuKVpp h4oxCqGpfC6D5l+Fn4rHYaYOHhdPvmlEps+ei3+CzCtgNBnnO0KYlkQqWQUXOPCK XOUwqSi4b6MiHTiRWDuJFQjy4iY9Asr0VQB9/hkz4IFwkpEi4uI3+8KQUYAH/EGi a0RHqBCDEXxGNUOmhRpslSda0u5oug+4FDT2dLX+M0gHpQR3IykGjRZl2KkFkM88 eNXriwUi9e7Buyzm8iquvEvVzsheWjCFDdMYdmFToPL3U5NwJibICfL+Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=qTmPCH+CX6Jgx+qfdfVTpUbaytBSd+JA9aQhJ5aICag=; b=WWzBTEfN u0mQRFpmNxdhE9I33rYRVgWNLdbDtPxVGj02tJAvz+cDiDZd+Q9AE+Qq2Nr7yCVs BGaTCBKb6e+jM1sX1yOG4VAR24C7rIyzRZCt57ROnTRr/+oj6sALdyC8MG/Ufh/p 63HQeNPVA//js1iC0AnVB9d6srksUtjKDSXqS2r1MykXN4e1idOELlxyusKfQsRF f+bf2Orpy4+njEKIY87fm6mEmwXbJ5DH7tmi/qjoD1ony8ZTtEncUBDeBfOWX5T9 AoiezxAofpirK1at+JkDgypn3CUzWJ85UWwxtn/yPwRic2oGoeFzVOQmsBkdsjjb aMe960OZLlF40A== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrudduiedgtdejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepvdehgfeivdejgedtveehfefhteelfefgieevgfffveefjeegtdfg uedthedtgeevnecukfhppeejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghruf hiiigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghl ohhnrdhnvght X-ME-Proxy: Received: from xps.monjalon.net (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id AD3C61080067; Tue, 9 Mar 2021 04:48:57 -0500 (EST) From: Thomas Monjalon To: dev@dpdk.org Cc: Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Date: Tue, 9 Mar 2021 10:48:36 +0100 Message-Id: <20210309094836.988763-5-thomas@monjalon.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210309094836.988763-1-thomas@monjalon.net> References: <20210308222855.823670-1-thomas@monjalon.net> <20210309094836.988763-1-thomas@monjalon.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 4/4] net/mlx5: reduce log level of alignment message X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Having to force an alignment does not impact the user, so it should not be a warning. The log level is reduced from warning to debug. Signed-off-by: Thomas Monjalon --- drivers/net/mlx5/mlx5_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c index 07373bff02..a39b5edddc 100644 --- a/drivers/net/mlx5/mlx5_utils.c +++ b/drivers/net/mlx5/mlx5_utils.c @@ -40,8 +40,8 @@ mlx5_hlist_create(const char *name, uint32_t size, uint32_t entry_size, /* Align to the next power of 2, 32bits integer is enough now. */ if (!rte_is_power_of_2(size)) { act_size = rte_align32pow2(size); - DRV_LOG(WARNING, "Size 0x%" PRIX32 " is not power of 2, will " - "be aligned to 0x%" PRIX32 ".", size, act_size); + DRV_LOG(DEBUG, "Size 0x%" PRIX32 " is not power of 2, " + "will be aligned to 0x%" PRIX32 ".", size, act_size); } else { act_size = size; } -- 2.30.1