From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22599A0524; Sun, 14 Mar 2021 13:13:16 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69191160857; Sun, 14 Mar 2021 13:13:15 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id A97D44067A for ; Sun, 14 Mar 2021 13:13:13 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 14 Mar 2021 14:13:12 +0200 Received: from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12ECD9X0023257; Sun, 14 Mar 2021 14:13:12 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org Date: Sun, 14 Mar 2021 12:13:01 +0000 Message-Id: <20210314121302.5988-5-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210314121302.5988-1-viacheslavo@nvidia.com> References: <20210307100251.22538-1-viacheslavo@nvidia.com> <20210314121302.5988-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 4/5] regex/mlx5: add timestamp format support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.1000 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for newly added fields cause the queue creation to fail. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 92f2c6a30fe0 ("regex/mlx5: add send queue") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad Acked-by: Ori Kam --- drivers/regex/mlx5/mlx5_regex.c | 1 + drivers/regex/mlx5/mlx5_regex.h | 1 + drivers/regex/mlx5/mlx5_regex_control.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index f1fd911405..ac5b205fa9 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -160,6 +160,7 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, rte_errno = ENOMEM; goto dev_error; } + priv->sq_ts_format = attr.sq_ts_format; priv->ctx = ctx; priv->nb_engines = 2; /* attr.regexp_num_of_engines */ ret = mlx5_devx_regex_register_read(priv->ctx, 0, diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 484819c38c..a2b3f0d9f3 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -70,6 +70,7 @@ struct mlx5_regex_priv { struct ibv_pd *pd; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ uint8_t is_bf2; /* The device is BF2 device. */ + uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ }; /* mlx5_regex.c */ diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index df57fada5d..55fbb419ed 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -158,6 +158,7 @@ regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, .wq_attr = (struct mlx5_devx_wq_attr){ .uar_page = priv->uar->page_id, }, + .ts_format = mlx5_ts_format_conv(priv->sq_ts_format), }; struct mlx5_devx_modify_sq_attr modify_attr = { .state = MLX5_SQC_STATE_RDY, -- 2.28.0