From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 222C7A054F; Tue, 16 Mar 2021 11:52:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E5012428AF; Tue, 16 Mar 2021 11:52:07 +0100 (CET) Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id 2CBFE242806 for ; Tue, 16 Mar 2021 11:52:02 +0100 (CET) X-QQ-mid: bizesmtp11t1615891918t77ixqvy Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Tue, 16 Mar 2021 18:51:57 +0800 (CST) X-QQ-SSF: 01400000002000C0E000B00A0000000 X-QQ-FEAT: x/IOQElPckInTUDUMl80k8awLF9DUe81qc5tqj5WVkg4xOs4xNnyEr6BrFZOG hJqbUKp4owWGcJnyhyLIWx8rj9+m2OSLQIT1vC32SdyPLrOGGvKgQjhc71TcSc3Hzt6PVli pTsyK8HifoRLF6hmS9gaEeaWWPhH8JD85oVvFg6B4aP5T7jx6OV+HmAj2PqUIP89VewKr+p aG9FYFbQ8KJyFeMtlOCEZUlJzHsEvP8ICUGo/13EBeYg6n0fXUH0xsDtRlE0eWZU/vcjOv6 O3saXhYhKuo81H3DFHUW4wr5+XhySe787CWQhs7W4sLs3WHtbbU8FPPISHc7Fh4E672ANJ/ UefuSOTBeIdmQDUmHIplIuNM6Ptv9NtPLOEwfhM X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Tue, 16 Mar 2021 18:51:49 +0800 Message-Id: <20210316105149.110904-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316105149.110904-1-jiawenwu@trustnetic.com> References: <20210316105149.110904-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign7 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v2 7/7] net/txgbe: add FFE parameters for user debugging X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support to set PHY link mode by user defined. Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_hw.c | 11 ++++ drivers/net/txgbe/base/txgbe_phy.c | 98 +++++++++++++++++++++++++++++- drivers/net/txgbe/base/txgbe_phy.h | 10 +++ 3 files changed, 116 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 917bd947f..3e7f2f9a3 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2951,6 +2951,9 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw) DEBUGFUNC("txgbe_get_media_type_raptor"); + if (hw->phy.ffe_set) + txgbe_bp_mode_set(hw); + /* Detect if there is a copper PHY attached. */ switch (hw->phy.type) { case txgbe_phy_cu_unknown: @@ -3544,6 +3547,14 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) hw->mac.orig_autoc = autoc; } + if (hw->phy.ffe_set) { + /* Make sure phy power is up */ + msec_delay(50); + + /* A temporary solution to set phy */ + txgbe_set_phy_temp(hw); + } + /* Store the permanent mac address */ hw->mac.get_mac_addr(hw, hw->mac.perm_addr); diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 5402a064f..dabc346f5 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1513,6 +1513,15 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg) } else { wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1); } + + if (hw->phy.ffe_set == TXGBE_BP_M_KR) { + value = (0x1804 & ~0x3F3F); + value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } out: return err; } @@ -1710,7 +1719,14 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg) goto out; } - if (hw->fw_version <= TXGBE_FW_N_TXEQ) { + if (hw->phy.ffe_set == TXGBE_BP_M_KX4) { + value = (0x1804 & ~0x3F3F); + value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { value = (0x1804 & ~0x3F3F); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); @@ -1917,7 +1933,15 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw, goto out; } - if (hw->fw_version <= TXGBE_FW_N_TXEQ) { + if (hw->phy.ffe_set == TXGBE_BP_M_KX) { + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; + value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; + value |= hw->phy.ffe_post | (1 << 6); + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { value = (0x1804 & ~0x3F3F) | (24 << 8) | 4; wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); @@ -2144,7 +2168,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw, goto out; } - if (hw->fw_version <= TXGBE_FW_N_TXEQ) { + if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; + value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; + value |= hw->phy.ffe_post | (1 << 6); + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); value = (value & ~0x3F3F) | (24 << 8) | 4; wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); @@ -2318,6 +2350,66 @@ void txgbe_bp_down_event(struct txgbe_hw *hw) txgbe_set_link_to_kr(hw, 0); } +void txgbe_bp_mode_set(struct txgbe_hw *hw) +{ + if (hw->phy.ffe_set == TXGBE_BP_M_SFI) + hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP; + else if (hw->phy.ffe_set == TXGBE_BP_M_KR) + hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4; + else if (hw->phy.ffe_set == TXGBE_BP_M_KX4) + hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI; + else if (hw->phy.ffe_set == TXGBE_BP_M_KX) + hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII; +} + +void txgbe_set_phy_temp(struct txgbe_hw *hw) +{ + u32 value; + + if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { + BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n", + hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); + + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); + value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | + hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); + value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } + + if (hw->phy.ffe_set == TXGBE_BP_M_KR) { + BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n", + hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); + value = (0x1804 & ~0x3F3F); + value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + wr32_epcs(hw, 0x18035, 0x00FF); + wr32_epcs(hw, 0x18055, 0x00FF); + } + + if (hw->phy.ffe_set == TXGBE_BP_M_KX) { + BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n", + hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); + value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | + hw->phy.ffe_pre; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); + + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); + value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + + wr32_epcs(hw, 0x18035, 0x00FF); + wr32_epcs(hw, 0x18055, 0x00FF); + } +} + /** * txgbe_kr_handle - Handle the interrupt of auto-negotiation * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index d2f2b2f8e..56531c4f8 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -396,6 +396,14 @@ #define TXGBE_MD_PORT_CTRL 0xF001 #define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1) +#define TXGBE_BP_M_NULL 0 +#define TXGBE_BP_M_SFI 1 +#define TXGBE_BP_M_KR 2 +#define TXGBE_BP_M_KX4 3 +#define TXGBE_BP_M_KX 4 +#define TXGBE_BP_M_NAUTO 0 +#define TXGBE_BP_M_AUTO 1 + #ifndef CL72_KRTR_PRBS_MODE_EN #define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */ #endif @@ -454,6 +462,8 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, u8 eeprom_data); u64 txgbe_autoc_read(struct txgbe_hw *hw); void txgbe_autoc_write(struct txgbe_hw *hw, u64 value); +void txgbe_bp_mode_set(struct txgbe_hw *hw); +void txgbe_set_phy_temp(struct txgbe_hw *hw); void txgbe_bp_down_event(struct txgbe_hw *hw); s32 txgbe_kr_handle(struct txgbe_hw *hw); -- 2.27.0