From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09D57A034F; Sun, 21 Mar 2021 09:50:15 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D9441140E25; Sun, 21 Mar 2021 09:49:59 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD5EC140E24 for ; Sun, 21 Mar 2021 09:49:58 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12L8l9de014497 for ; Sun, 21 Mar 2021 01:49:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xexL9EgCec+AhX/xNk61JvLknszYN4ZPZbvjUq0MMXs=; b=dB1ofIoVPKY3anJ3RpNbrLmt4OTiLyN5n7FS9Y5UuPvwSqrhuYMitn7YXLo/l4Z4w7bQ lzTjTe5pEAnf46gdaQSbcl0CyOXj7bwTXc1bkZ3UjAAacgaaFdT5hbQdlWxPZXPMonMF D67wsrahVtvaSjaf10vZjTxQljYdU8rGbCY39/Mx4dZSPmVW1KjH7RoyrxOqc455O81Z eyQB+spWqAYB6WoAk8PV9ukVETDioGl2Ell9EZ5F33UIw310ff6bpK2gmXMusMb7Lq03 VQD86xJ1qAoI8sbfX+Y2Y1hRXLiyj90csCCxJcntMsosdQbswl/XWUPwwkMBi1JLTvfu TQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37dgjnsrkw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 21 Mar 2021 01:49:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 21 Mar 2021 01:49:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 21 Mar 2021 01:49:55 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 150113F703F; Sun, 21 Mar 2021 01:49:54 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 21 Mar 2021 14:19:13 +0530 Message-ID: <20210321084915.2649-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210321084915.2649-1-pbhagavatula@marvell.com> References: <20210225122315.6350-1-pbhagavatula@marvell.com> <20210321084915.2649-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-20_13:2021-03-19, 2021-03-20 signatures=0 Subject: [dpdk-dev] [PATCH v2 3/4] event/octeontx2: reduce chunk pool memory usage X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Reduce amount of memory used by chunk pool when the mempool used is OCTEONTX2 NPA. Previously, the number of chunks configured when NPA is used is equal to the number of timers requested plus the number of buckets and if the max timeout is long enough w.r.t. resolution requested there will a large number of buckets which would cause high memory usage. Reduce the number of chunks when NPA is used to the number of timers requested as buckets that are processed chunk lists are automatically freed. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 19 ++++++++++--------- drivers/event/octeontx2/otx2_tim_evdev.h | 2 +- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index d1e967eb7..4fb002ddb 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -91,6 +91,8 @@ tim_chnk_pool_create(struct otx2_tim_ring *tim_ring, if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE) cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; + cache_sz = cache_sz != 0 ? cache_sz : 2; + tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); if (!tim_ring->disable_npa) { tim_ring->chunk_pool = rte_mempool_create_empty(pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, @@ -268,16 +270,15 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) } } - tim_ring->nb_chunks = tim_ring->nb_timers / OTX2_TIM_NB_CHUNK_SLOTS( - tim_ring->chunk_sz); - tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); - - if (tim_ring->disable_npa) + if (tim_ring->disable_npa) { + tim_ring->nb_chunks = + tim_ring->nb_timers / + OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts; - else - tim_ring->nb_chunks = tim_ring->nb_chunks + tim_ring->nb_bkts; - - /* Create buckets. */ + } else { + tim_ring->nb_chunks = tim_ring->nb_timers; + } + tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) * sizeof(struct otx2_tim_bkt), RTE_CACHE_LINE_SIZE); diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index bf89b85b0..0667d4576 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -70,7 +70,7 @@ #define OTX2_TIM_MAX_BURST (RTE_CACHE_LINE_SIZE / \ OTX2_TIM_CHUNK_ALIGNMENT) #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1) -#define OTX2_TIM_MIN_CHUNK_SLOTS (0x1) +#define OTX2_TIM_MIN_CHUNK_SLOTS (0x8) #define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE) #define OTX2_TIM_MIN_TMO_TKS (256) -- 2.17.1