From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8A61A0562; Tue, 23 Mar 2021 09:45:10 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 75545140D1E; Tue, 23 Mar 2021 09:44:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 73E56140D1C for ; Tue, 23 Mar 2021 09:44:56 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12N8ZLjk021392 for ; Tue, 23 Mar 2021 01:44:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/UaWKgL5JKsdVzuFK5WgfUsmVEDTI05gNnSsWKSxvSI=; b=Lt466RdWHVKTqjFarLXhwjUvcjGVb1EWOWGoM8HsDuFvTuJ0E9aiuJZjRpPvxPkD7yCj MNFGlSAxp/2O494sdOLOXsgMKe7FDqMKqEZ8kTVHfBlgr9p43LDty4cTcdeR1deyIlnV t8Zf6oFp6xsYxxvMCtn8ypSyIww+b6IC+djge+LUXO5Us1IgNwMTjhzg3kAC94gE+m/+ I3LsA/SShafRqJbD6NMI31zGnoFfXb2boSnRH29euFPuBN7dig8pzI7p+uYEBrIEQlGO sSka7hF3yc1Ku97EDKk7cDHzYmrXsBrRebmgZp4pcfnE96urNrv0L+RLHfOA9a91pJ7s ag== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 37dedrgdnn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 23 Mar 2021 01:44:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 01:44:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 01:44:54 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 1E7913F703F; Tue, 23 Mar 2021 01:44:52 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Tue, 23 Mar 2021 14:14:38 +0530 Message-ID: <20210323084439.3898-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210323084439.3898-1-pbhagavatula@marvell.com> References: <20210321084915.2649-1-pbhagavatula@marvell.com> <20210323084439.3898-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-23_02:2021-03-22, 2021-03-23 signatures=0 Subject: [dpdk-dev] [PATCH v3 4/4] event/octeontx2: timer always use virtual counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Use virtual counter for estimating current bucket as PMU cannot be reliably used to estimate time. Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Use __rte_arm64_cntvct and __rte_arm64_cntfrq instead of reimplementing asm. drivers/event/octeontx2/otx2_tim_evdev.c | 19 +++-------------- drivers/event/octeontx2/otx2_tim_evdev.h | 26 +++++++++++++++++++++++ drivers/event/octeontx2/otx2_tim_worker.c | 4 ++-- drivers/event/octeontx2/otx2_tim_worker.h | 2 +- 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 4fb002ddb..926c2dce6 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -354,7 +354,7 @@ otx2_tim_calibrate_start_tsc(struct otx2_tim_ring *tim_ring) for (icount = 0; icount < OTX2_TIM_CALIB_ITER; icount++) { real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; - bkt_cyc = rte_rdtsc(); + bkt_cyc = tim_cntvct(); bucket = (bkt_cyc - tim_ring->ring_start_cyc) / tim_ring->tck_int; bucket = bucket % (tim_ring->nb_bkts); @@ -389,20 +389,8 @@ otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr) tim_err_desc(rc); goto fail; } -#ifdef RTE_ARM_EAL_RDTSC_USE_PMU - uint64_t tenns_stmp, tenns_diff; - uint64_t pmu_stmp; - - pmu_stmp = rte_rdtsc(); - asm volatile("mrs %0, cntvct_el0" : "=r" (tenns_stmp)); - - tenns_diff = tenns_stmp - rsp->timestarted; - pmu_stmp = pmu_stmp - (NSEC2TICK(tenns_diff * 10, rte_get_timer_hz())); - tim_ring->ring_start_cyc = pmu_stmp; -#else tim_ring->ring_start_cyc = rsp->timestarted; -#endif - tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, rte_get_timer_hz()); + tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, tim_cntfrq()); tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts); @@ -470,8 +458,7 @@ otx2_tim_stats_get(const struct rte_event_timer_adapter *adapter, struct rte_event_timer_adapter_stats *stats) { struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv; - uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc; - + uint64_t bkt_cyc = tim_cntvct() - tim_ring->ring_start_cyc; stats->evtim_exp_count = __atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED); diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 0667d4576..410880e14 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -176,6 +176,32 @@ tim_priv_get(void) return mz->addr; } +#ifdef RTE_ARCH_ARM64 +static inline uint64_t +tim_cntvct(void) +{ + return __rte_arm64_cntvct(); +} + +static inline uint64_t +tim_cntfrq(void) +{ + return __rte_arm64_cntfrq(); +} +#else +static inline uint64_t +tim_cntvct(void) +{ + return 0; +} + +static inline uint64_t +tim_cntfrq(void) +{ + return 0; +} +#endif + #define TIM_ARM_FASTPATH_MODES \ FP(sp, 0, 0, 0, OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \ FP(mp, 0, 0, 1, OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \ diff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c index 6a3511ec0..9ee07958f 100644 --- a/drivers/event/octeontx2/otx2_tim_worker.c +++ b/drivers/event/octeontx2/otx2_tim_worker.c @@ -41,12 +41,12 @@ tim_format_event(const struct rte_event_timer * const tim, static inline void tim_sync_start_cyc(struct otx2_tim_ring *tim_ring) { - uint64_t cur_cyc = rte_rdtsc(); + uint64_t cur_cyc = tim_cntvct(); uint32_t real_bkt; if (cur_cyc - tim_ring->last_updt_cyc > tim_ring->tot_int) { real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; - cur_cyc = rte_rdtsc(); + cur_cyc = tim_cntvct(); tim_ring->ring_start_cyc = cur_cyc - (real_bkt * tim_ring->tck_int); diff --git a/drivers/event/octeontx2/otx2_tim_worker.h b/drivers/event/octeontx2/otx2_tim_worker.h index 5ece8fd05..efe88a869 100644 --- a/drivers/event/octeontx2/otx2_tim_worker.h +++ b/drivers/event/octeontx2/otx2_tim_worker.h @@ -132,7 +132,7 @@ tim_get_target_bucket(struct otx2_tim_ring *const tim_ring, const uint32_t rel_bkt, struct otx2_tim_bkt **bkt, struct otx2_tim_bkt **mirr_bkt) { - const uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc; + const uint64_t bkt_cyc = tim_cntvct() - tim_ring->ring_start_cyc; uint64_t bucket = rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div) + rel_bkt; -- 2.17.1