From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 457B2A0A02; Thu, 25 Mar 2021 05:32:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 01999140E48; Thu, 25 Mar 2021 05:32:46 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id ED659140E45 for ; Thu, 25 Mar 2021 05:32:44 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 25 Mar 2021 06:32:42 +0200 Received: from nvidia.com (mtbc-r640-03.mtbc.labs.mlnx [10.75.70.8]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12P4Wbvl031494; Thu, 25 Mar 2021 06:32:41 +0200 From: Suanming Mou To: orika@nvidia.com Cc: dev@dpdk.org, viacheslavo@nvidia.com, matan@nvidia.com, rasland@nvidia.com Date: Thu, 25 Mar 2021 06:32:33 +0200 Message-Id: <20210325043236.964312-2-suanmingm@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210325043236.964312-1-suanmingm@nvidia.com> References: <20210309235732.3952418-1-suanmingm@nvidia.com> <20210325043236.964312-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 1/4] common/mlx5: add user memory registration bits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds the UMR capability bits. Signed-off-by: Suanming Mou --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ 3 files changed, 10 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 220de35420..5d6a861689 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -186,6 +186,8 @@ has_sym_args = [ 'mlx5dv_dr_action_create_aso' ], [ 'HAVE_INFINIBAND_VERBS_H', 'infiniband/verbs.h', 'INFINIBAND_VERBS_H' ], + [ 'HAVE_MLX5_UMR_IMKEY', 'infiniband/mlx5dv.h', + 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ], ] config = configuration_data() foreach arg:has_sym_args diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c90e020643..268bcd0d99 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -266,6 +266,7 @@ mlx5_devx_cmd_mkey_create(void *ctx, MLX5_SET(mkc, mkc, qpn, 0xffffff); MLX5_SET(mkc, mkc, pd, attr->pd); MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); + MLX5_SET(mkc, mkc, umr_en, attr->umr_en); MLX5_SET(mkc, mkc, translations_octword_size, translation_size); MLX5_SET(mkc, mkc, relaxed_ordering_write, attr->relaxed_ordering_write); @@ -752,6 +753,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, mini_cqe_resp_flow_tag); attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_l3_l4_tag); + attr->umr_indirect_mkey_disabled = + MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); + attr->umr_modify_entity_size_disabled = + MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 2826c0b2c6..67b5f771c6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -31,6 +31,7 @@ struct mlx5_devx_mkey_attr { uint32_t pg_access:1; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; + uint32_t umr_en:1; struct mlx5_klm *klm_array; int klm_num; }; @@ -151,6 +152,8 @@ struct mlx5_hca_attr { uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; uint32_t log_max_mmo_decompress:5; + uint32_t umr_modify_entity_size_disabled:1; + uint32_t umr_indirect_mkey_disabled:1; }; struct mlx5_devx_wq_attr { -- 2.25.1