From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7363A0A02; Thu, 25 Mar 2021 06:52:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F220140EC2; Thu, 25 Mar 2021 06:52:03 +0100 (CET) Received: from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102]) by mails.dpdk.org (Postfix) with ESMTP id CBF82140EAC for ; Thu, 25 Mar 2021 06:51:57 +0100 (CET) X-QQ-mid: bizesmtp19t1616651511talw148j Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Thu, 25 Mar 2021 13:51:51 +0800 (CST) X-QQ-SSF: 01400000000000D0E000000A0000000 X-QQ-FEAT: X+Lnu8pJYlfHO6l+lsL6D5Lu4sNbUXFAZPINKR6OZVDGqUXCip9n2ItAficBI pn9KUmULrEpUhYJANVQbcpdQuK6QoEY6vwaJ+BgMDw2OHZCRChdiM8YA0zzrC60NMsq4ZbW 20Jft+4oeiWR7dJlqeBfuh5blleQlq2AtSaJMkKixfydh1XVPpe0CEK9w/CsgJyN2h1E6U3 t04u7L+5r6U5KqU4t4etgWyDgjX+aGamBEvDCfdnQANqAfBz5gjJWAROMxhoSMfxD9iWNFu le7seCbAc5i6CkNG73Og1UViplxlw6xGAmwrpJmXQnPaY35oaE7tJYYfe3fOUHTeiQXP3QT ag27v/BgG4H1OfFUyhm56uZObfM5A== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Thu, 25 Mar 2021 13:51:38 +0800 Message-Id: <20210325055141.629963-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210325055141.629963-1-jiawenwu@trustnetic.com> References: <20210325055141.629963-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v3 4/7] net/txgbe/base: support to handle backplane AN73 flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Suppot to handle the interrupt of auto-negotiation, improve the link training process of connecting with other switches. Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_hw.c | 3 + drivers/net/txgbe/base/txgbe_phy.c | 461 +++++++++++++++++++++++++++- drivers/net/txgbe/base/txgbe_phy.h | 5 + drivers/net/txgbe/base/txgbe_type.h | 9 + 4 files changed, 476 insertions(+), 2 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 521cb4650..9a82a329a 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2574,6 +2574,9 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) txgbe_get_copper_link_capabilities; } + if (phy->media_type == txgbe_media_type_backplane) + mac->kr_handle = txgbe_kr_handle; + /* Set necessary function pointers based on PHY type */ switch (hw->phy.type) { case txgbe_phy_tn: diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 33d3839ed..140857121 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -9,6 +9,17 @@ static void txgbe_i2c_start(struct txgbe_hw *hw); static void txgbe_i2c_stop(struct txgbe_hw *hw); +static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw); +static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, + u32 link_partner, struct txgbe_hw *hw); +static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, + struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw); +static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw); +static s32 txgbe_enable_kr_training(struct txgbe_hw *hw); +static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode); +static s32 txgbe_check_kr_training(struct txgbe_hw *hw); +static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, + s32 post, s32 mode); static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed); /** @@ -1399,7 +1410,7 @@ static void txgbe_i2c_stop(struct txgbe_hw *hw) wr32(hw, TXGBE_I2CENA, 0); } -static s32 +static void txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) { u32 value; @@ -1410,7 +1421,6 @@ txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) value = rd32_epcs(hw, SR_MII_MMD_CTL); value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9); wr32_epcs(hw, SR_MII_MMD_CTL, value); - return 0; } static s32 @@ -2294,3 +2304,450 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc) mactxcfg | TXGBE_MACTXCFG_TXE); } +/** + * txgbe_kr_handle - Handle the interrupt of auto-negotiation + * @hw: pointer to hardware structure + */ +s32 txgbe_kr_handle(struct txgbe_hw *hw) +{ + u32 value; + s32 status = 0; + + DEBUGFUNC("txgbe_kr_handle"); + + value = rd32_epcs(hw, VR_AN_INTR); + BP_LOG("AN INTERRUPT!! value: 0x%x\n", value); + if (!(value & VR_AN_INTR_PG_RCV)) { + wr32_epcs(hw, VR_AN_INTR, 0); + return status; + } + + status = txgbe_handle_bp_flow(0, hw); + + return status; +} + +/** + * txgbe_handle_bp_flow - Handle backplane AN73 flow + * @hw: pointer to hardware structure + * @link_mode: local AN73 link mode + */ +static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw) +{ + u32 value, i, lp_reg, ld_reg; + s32 status = 0; + struct txgbe_backplane_ability local_ability, lp_ability; + + DEBUGFUNC("txgbe_handle_bp_flow"); + + local_ability.current_link_mode = link_mode; + + /* 1. Get the local AN73 Base Page Ability */ + BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n"); + txgbe_get_bp_ability(&local_ability, 0, hw); + + /* 2. Check and clear the AN73 Interrupt Status */ + BP_LOG("<2>. Check the AN73 Interrupt Status ...\n"); + txgbe_clear_bp_intr(2, 0, hw); + + /* 3.1. Get the link partner AN73 Base Page Ability */ + BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n"); + txgbe_get_bp_ability(&lp_ability, 1, hw); + + /* 3.2. Check the AN73 Link Ability with Link Partner */ + BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n"); + BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability); + BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability); + + status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw); + + wr32_epcs(hw, SR_AN_CTRL, 0); + wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); + + /* 3.3. Check the FEC and KR Training for KR mode */ + BP_LOG("<3.3>. Check the FEC for KR mode ...\n"); + if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) { + BP_LOG("Enable the Backplane KR FEC ...\n"); + wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN); + } else { + BP_LOG("Backplane KR FEC is disabled.\n"); + } + + printf("Enter training.\n"); + /* CL72 KR training on */ + for (i = 0; i < 2; i++) { + /* 3.4. Check the CL72 KR Training for KR mode */ + BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n"); + BP_LOG("==================%d==================\n", i); + status = txgbe_enable_kr_training(hw); + BP_LOG("Check the Clause 72 KR Training status ...\n"); + status |= txgbe_check_kr_training(hw); + + lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); + lp_reg &= SR_PMA_KR_LP_CESTS_RR; + BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", + lp_reg); + ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); + ld_reg &= SR_PMA_KR_LD_CESTS_RR; + BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n", + ld_reg); + if (hw->devarg.poll == 0 && status != 0) + lp_reg = SR_PMA_KR_LP_CESTS_RR; + + if (lp_reg & ld_reg) { + BP_LOG("==================out==================\n"); + status = txgbe_disable_kr_training(hw, 0, 0); + wr32_epcs(hw, SR_AN_CTRL, 0); + txgbe_clear_bp_intr(2, 0, hw); + txgbe_clear_bp_intr(1, 0, hw); + txgbe_clear_bp_intr(0, 0, hw); + for (i = 0; i < 10; i++) { + value = rd32_epcs(hw, SR_XS_PCS_KR_STS1); + if (value & SR_XS_PCS_KR_STS1_PLU) { + BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n"); + wr32_epcs(hw, SR_AN_CTRL, 0); + return 0; + } + msec_delay(10); + } + msec_delay(1000); + txgbe_set_link_to_kr(hw, 0); + + return 0; + } + + status |= txgbe_disable_kr_training(hw, 0, 0); + } + + txgbe_clear_bp_intr(2, 0, hw); + txgbe_clear_bp_intr(1, 0, hw); + txgbe_clear_bp_intr(0, 0, hw); + + return status; +} + +/** + * txgbe_get_bp_ability + * @hw: pointer to hardware structure + * @ability: pointer to blackplane ability structure + * @link_partner: + * 1: Get Link Partner Base Page + * 2: Get Link Partner Next Page + * (only get NXP Ability Register 1 at the moment) + * 0: Get Local Device Base Page + */ +static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, + u32 link_partner, struct txgbe_hw *hw) +{ + u32 value = 0; + + DEBUGFUNC("txgbe_get_bp_ability"); + + /* Link Partner Base Page */ + if (link_partner == 1) { + /* Read the link partner AN73 Base Page Ability Registers */ + BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n"); + value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1); + BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n", + value); + ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value); + BP_LOG(" Next Page (bit15): %d\n", ability->next_page); + + value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2); + BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n", + value); + ability->link_ability = + value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX; + BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", + ability->link_ability); + BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); + BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); + + value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3); + BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n", + value); + BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); + BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); + ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value); + } else if (link_partner == 2) { + /* Read the link partner AN73 Next Page Ability Registers */ + BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n"); + value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1); + BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value); + ability->next_page = SR_AN_LP_XNP_ABL1_NP(value); + BP_LOG(" Next Page (bit15): %d\n", ability->next_page); + } else { + /* Read the local AN73 Base Page Ability Registers */ + BP_LOG("Read the local AN73 Base Page Ability Registers...\n"); + value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1); + BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value); + ability->next_page = SR_AN_MMD_ADV_REG1_NP(value); + BP_LOG(" Next Page (bit15): %d\n", ability->next_page); + + value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2); + BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value); + ability->link_ability = + value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX; + BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", + ability->link_ability); + BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); + BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); + + value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3); + BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value); + BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); + BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); + ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value); + } + + BP_LOG("done.\n"); +} + +/** + * txgbe_check_bp_ability + * @hw: pointer to hardware structure + * @ability: pointer to blackplane ability structure + */ +static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, + struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw) +{ + u32 com_link_abi; + s32 ret = 0; + + DEBUGFUNC("txgbe_check_bp_ability"); + + com_link_abi = local_ability->link_ability & lp_ability->link_ability; + BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n", + com_link_abi, local_ability->link_ability, + lp_ability->link_ability); + + if (!com_link_abi) { + BP_LOG("The Link Partner does not support any compatible speed mode.\n"); + ret = -1; + } else if (com_link_abi & BP_TYPE_KR) { + if (local_ability->current_link_mode) { + BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n"); + BP_LOG("Set the local link mode to [LINK_KR] ...\n"); + txgbe_set_link_to_kr(hw, 0); + ret = 1; + } else { + BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n"); + ret = 0; + } + } else if (com_link_abi & BP_TYPE_KX4) { + if (local_ability->current_link_mode == 0x10) { + BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n"); + ret = 0; + } else { + BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n"); + BP_LOG("Set the local link mode to [LINK_KX4] ...\n"); + txgbe_set_link_to_kx4(hw, 1); + ret = 1; + } + } else if (com_link_abi & BP_TYPE_KX) { + if (local_ability->current_link_mode == 0x1) { + BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n"); + ret = 0; + } else { + BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n"); + BP_LOG("Set the local link mode to [LINK_KX] ...\n"); + txgbe_set_link_to_kx(hw, 1, 1); + ret = 1; + } + } + + return ret; +} + +/** + * txgbe_clear_bp_intr + * @hw: pointer to hardware structure + * @index: the bit will be cleared + * @index_high: + * index_high = 0: Only the index bit will be cleared + * index_high != 0: the [index_high, index] range will be cleared + */ +static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw) +{ + u32 rdata = 0, wdata, i; + + DEBUGFUNC("txgbe_clear_bp_intr"); + + rdata = rd32_epcs(hw, VR_AN_INTR); + BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n", + rdata); + BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n"); + + wdata = rdata; + if (bit_high) { + for (i = bit; i <= bit_high; i++) + wdata &= ~(1 << i); + } else { + wdata &= ~(1 << bit); + } + + wr32_epcs(hw, VR_AN_INTR, wdata); + + rdata = rd32_epcs(hw, VR_AN_INTR); + BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata); +} + +static s32 txgbe_enable_kr_training(struct txgbe_hw *hw) +{ + s32 status = 0; + u32 value = 0; + + DEBUGFUNC("txgbe_enable_kr_training"); + + BP_LOG("Enable Clause 72 KR Training ...\n"); + + if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) { + /* Set PRBS Timer Duration Control to maximum 6.7ms in + * VR_PMA_KRTR_PRBS_CTRL2 Register + */ + value = CL72_KRTR_PRBS_MODE_EN; + wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value); + /* Set PRBS Timer Duration Control to maximum 6.7ms in + * VR_PMA_KRTR_PRBS_CTRL1 Register + */ + wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1, + VR_PMA_KRTR_PRBS_TIME_LMT); + /* Enable PRBS Mode to determine KR Training Status by setting + * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register + */ + value = VR_PMA_KRTR_PRBS_MODE_EN; + } +#ifdef CL72_KRTR_PRBS31_EN + /* Enable PRBS Mode to determine KR Training Status by setting + * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register + */ + value = VR_PMA_KRTR_PRBS31_EN; +#endif + wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value); + /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ + txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); + + /* Enable the Clause 72 start-up protocol + * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register. + * Restart the Clause 72 start-up protocol + * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register. + */ + wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, + SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR); + + return status; +} + +static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode) +{ + s32 status = 0; + + DEBUGFUNC("txgbe_disable_kr_training"); + + BP_LOG("Disable Clause 72 KR Training ...\n"); + /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ + txgbe_read_phy_lane_tx_eq(0, hw, post, mode); + + wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR); + + return status; +} + +static s32 txgbe_check_kr_training(struct txgbe_hw *hw) +{ + s32 status = 0; + u32 value, test; + int i; + int times = hw->devarg.poll ? 35 : 20; + + DEBUGFUNC("txgbe_check_kr_training"); + + for (i = 0; i < times; i++) { + value = rd32_epcs(hw, SR_PMA_KR_LP_CEU); + BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n", + value); + value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); + BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", + value); + value = rd32_epcs(hw, SR_PMA_KR_LD_CEU); + BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n", + value); + value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); + BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n", + value); + value = rd32_epcs(hw, SR_PMA_KR_PMD_STS); + BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value); + BP_LOG(" Training Failure (bit3): %d\n", + ((value >> 3) & 0x01)); + BP_LOG(" Start-Up Protocol Status (bit2): %d\n", + ((value >> 2) & 0x01)); + BP_LOG(" Frame Lock (bit1): %d\n", + ((value >> 1) & 0x01)); + BP_LOG(" Receiver Status (bit0): %d\n", + ((value >> 0) & 0x01)); + + test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); + if (test & SR_PMA_KR_LP_CESTS_RR) { + BP_LOG("TEST Coefficient Status Register: 0x%x\n", + test); + status = 1; + } + + if (value & SR_PMA_KR_PMD_STS_TR_FAIL) { + BP_LOG("Training is completed with failure.\n"); + txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); + return 0; + } + + if (value & SR_PMA_KR_PMD_STS_RCV) { + BP_LOG("Receiver trained and ready to receive data.\n"); + txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); + return 0; + } + + msec_delay(20); + } + + BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n"); + return status; +} + +static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, + s32 post, s32 mode) +{ + u32 value = 0; + u32 addr; + u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain; + + DEBUGFUNC("txgbe_read_phy_lane_tx_eq"); + + addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8); + value = rd32_ephy(hw, addr); + BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane); + tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value); + BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor); + UNREFERENCED_PARAMETER(tx_main_cursor); + + addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8); + value = rd32_ephy(hw, addr); + tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE; + tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value); + BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor); + BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor); + + if (mode == 1) { + lmain = 160 - tx_pre_cursor - tx_post_cursor; + if (lmain < 88) + lmain = 88; + + if (post) + tx_post_cursor = post; + + wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor); + wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0, + tx_pre_cursor | (lmain << 8)); + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); + value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF; + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); + } +} diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index b804d2406..ad4a915f8 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -396,6 +396,10 @@ #define TXGBE_MD_PORT_CTRL 0xF001 #define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1) +#ifndef CL72_KRTR_PRBS_MODE_EN +#define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */ +#endif + /****************************************************************************** * SFP I2C Registers: ******************************************************************************/ @@ -450,5 +454,6 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, u8 eeprom_data); u64 txgbe_autoc_read(struct txgbe_hw *hw); void txgbe_autoc_write(struct txgbe_hw *hw, u64 value); +s32 txgbe_kr_handle(struct txgbe_hw *hw); #endif /* _TXGBE_PHY_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 33572cc3c..0ce469212 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -600,6 +600,8 @@ struct txgbe_mac_info { s32 (*dmac_config)(struct txgbe_hw *hw); s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee); + s32 (*kr_handle)(struct txgbe_hw *hw); + enum txgbe_mac_type type; u8 addr[ETH_ADDR_LEN]; u8 perm_addr[ETH_ADDR_LEN]; @@ -795,6 +797,13 @@ struct txgbe_hw { } qp_last[TXGBE_MAX_QP]; }; +struct txgbe_backplane_ability { + u32 next_page; /* Next Page (bit0) */ + u32 link_ability; /* Link Ability (bit[7:0]) */ + u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */ + u32 current_link_mode; /* current link mode for local device */ +}; + #include "txgbe_regs.h" #include "txgbe_dummy.h" -- 2.27.0