From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80C82A0548; Thu, 1 Apr 2021 11:48:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 574B6140E19; Thu, 1 Apr 2021 11:48:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 93029140E10 for ; Thu, 1 Apr 2021 11:48:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1319fDCA014965 for ; Thu, 1 Apr 2021 02:48:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=A3+5kDaYb7NHNInylVlUjFAaR98F7yqWwYWxTAFs8yE=; b=k/2PLXQIHWmU5uKDL9b5q00LkbDdBneIypEbowPdmkp/mwTn+dWaowZuIElHlq7GLIPW +bf3RhRuCePlO93NUtN6m6yVNhWX33+i9U8tcOSmgBBMmd6lc+z7Qpag7FOpL1sBjM1k 3/UbEXSDFJsK+CcknDeKDDtqZGmlNMWMl11i5dBZWn3DYgwUfG4suKhHEZlLlE+Ivcd3 nXRxAcQiT5oKhvQL2avak6WI9v9Cd+kEJoX3NMVxeypU6IXFGievbHX2lFb8SGE6Xjjt ZgEQr/w+ytkjqlWbdScRVe/9frZ9jcPxFS5vbceDRgo9i2dIdP5Gyx3FH4/PCyxu2rLt iA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37n28j1wkk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Apr 2021 02:48:10 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 02:48:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 02:48:08 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 864A63F7040; Thu, 1 Apr 2021 02:48:04 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Nithin Dabilpuram Date: Thu, 1 Apr 2021 15:16:48 +0530 Message-ID: <20210401094739.22714-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210401094739.22714-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210401094739.22714-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: S5Jldjm_y1SrNyJju6uw8iDHmKy9SjTS X-Proofpoint-GUID: S5Jldjm_y1SrNyJju6uw8iDHmKy9SjTS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_04:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v2 01/52] doc: add Marvell CNXK platform guide X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Platform specific guide for Marvell OCTEON CN9K/CN10K SoC is added. Signed-off-by: Nithin Dabilpuram Signed-off-by: Jerin Jacob --- MAINTAINERS | 9 + doc/guides/platform/cnxk.rst | 578 ++++ .../img/cnxk_packet_flow_hw_accelerators.svg | 2795 ++++++++++++++++++++ .../platform/img/cnxk_resource_virtualization.svg | 2428 +++++++++++++++++ doc/guides/platform/index.rst | 1 + 5 files changed, 5811 insertions(+) create mode 100644 doc/guides/platform/cnxk.rst create mode 100644 doc/guides/platform/img/cnxk_packet_flow_hw_accelerators.svg create mode 100644 doc/guides/platform/img/cnxk_resource_virtualization.svg diff --git a/MAINTAINERS b/MAINTAINERS index 0f5e745..c466420 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -732,6 +732,15 @@ F: drivers/net/ipn3ke/ F: doc/guides/nics/ipn3ke.rst F: doc/guides/nics/features/ipn3ke.ini +Marvell cnxk +M: Nithin Dabilpuram +M: Kiran Kumar K +M: Sunil Kumar Kori +M: Satha Rao +T: git://dpdk.org/next/dpdk-next-net-mrvl +F: drivers/common/cnxk/ +F: doc/guides/platform/cnxk.rst + Marvell mvpp2 M: Liron Himi T: git://dpdk.org/next/dpdk-next-net-mrvl diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst new file mode 100644 index 0000000..3b07287 --- /dev/null +++ b/doc/guides/platform/cnxk.rst @@ -0,0 +1,578 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(C) 2021 Marvell. + +Marvell CNXK Platform Guide +=========================== + +This document gives an overview of **Marvell OCTEON CN9K and CN10K** RVU H/W block, +packet flow and procedure to build DPDK on OCTEON CNXK platform. + +More information about CN9K and CN10K SoC can be found at `Marvell Official Website +`_. + +Supported OCTEON CNXK SoCs +-------------------------- + +- CN106xx + +CNXK Resource Virtualization Unit architecture +---------------------------------------------- + +The :numref:`figure_cnxk_resource_virtualization` diagram depicts the +RVU architecture and a resource provisioning example. + +.. _figure_cnxk_resource_virtualization: + +.. figure:: img/cnxk_resource_virtualization.* + + CNXK Resource virtualization architecture and provisioning example + + +Resource Virtualization Unit (RVU) on Marvell's OCTEON CN9K/CN10K SoC maps HW +resources belonging to the network, crypto and other functional blocks onto +PCI-compatible physical and virtual functions. + +Each functional block has multiple local functions (LFs) for +provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV +physical functions (PFs) and virtual functions (VFs). + +The :numref:`table_cnxk_rvu_dpdk_mapping` shows the various local +functions (LFs) provided by the RVU and its functional mapping to +DPDK subsystem. + +.. _table_cnxk_rvu_dpdk_mapping: + +.. table:: RVU managed functional blocks and its mapping to DPDK subsystem + + +---+-----+--------------------------------------------------------------+ + | # | LF | DPDK subsystem mapping | + +===+=====+==============================================================+ + | 1 | NIX | rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security| + +---+-----+--------------------------------------------------------------+ + | 2 | NPA | rte_mempool | + +---+-----+--------------------------------------------------------------+ + | 3 | NPC | rte_flow | + +---+-----+--------------------------------------------------------------+ + | 4 | CPT | rte_cryptodev, rte_event_crypto_adapter | + +---+-----+--------------------------------------------------------------+ + | 5 | SSO | rte_eventdev | + +---+-----+--------------------------------------------------------------+ + | 6 | TIM | rte_event_timer_adapter | + +---+-----+--------------------------------------------------------------+ + | 7 | LBK | rte_ethdev | + +---+-----+--------------------------------------------------------------+ + | 8 | DPI | rte_rawdev | + +---+-----+--------------------------------------------------------------+ + | 9 | SDP | rte_ethdev | + +---+-----+--------------------------------------------------------------+ + | 10| REE | rte_regexdev | + +---+-----+--------------------------------------------------------------+ + +PF0 is called the administrative / admin function (AF) and has exclusive +privileges to provision RVU functional block's LFs to each of the PF/VF. + +PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving +requests from PF/VF, AF does resource provisioning and other HW configuration. + +AF is always attached to host, but PF/VFs may be used by host kernel itself, +or attached to VMs or to userspace applications like DPDK, etc. So, AF has to +handle provisioning/configuration requests sent by any device from any domain. + +The AF driver does not receive or process any data. +It is only a configuration driver used in control path. + +The :numref:`figure_cnxk_resource_virtualization` diagram also shows a +resource provisioning example where, + +1. PFx and PFx-VF0 bound to Linux netdev driver. +2. PFx-VF1 ethdev driver bound to the first DPDK application. +3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application. + +LBK HW Access +------------- + +Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX. +The loopback block has N channels and contains data buffering that is shared across +all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's +VFs are exposed as ethdev device and odd-even pairs of VFs are tied together, +that is, packets sent on odd VF end up received on even VF and vice versa. +This would enable HW accelerated means of communication between two domains +where even VF bound to the first domain and odd VF bound to the second domain. + +Typical application usage models are, + +#. Communication between the Linux kernel and DPDK application. +#. Exception path to Linux kernel from DPDK application as SW ``KNI`` replacement. +#. Communication between two different DPDK applications. + +SDP interface +------------- + +System DPI Packet Interface unit(SDP) provides PCIe endpoint support for remote host +to DMA packets into and out of CNXK SoC. SDP interface comes in to live only when +CNXK SoC is connected in PCIe endpoint mode. It can be used to send/receive +packets to/from remote host machine using input/output queue pairs exposed to it. +SDP interface receives input packets from remote host from NIX-RX and sends packets +to remote host using NIX-TX. Remote host machine need to use corresponding driver +(kernel/user mode) to communicate with SDP interface on CNXK SoC. SDP supports +single PCIe SRIOV physical function(PF) and multiple virtual functions(VF's). Users +can bind PF or VF to use SDP interface and it will be enumerated as ethdev ports. + +The primary use case for SDP is to enable the smart NIC use case. Typical usage models are, + +#. Communication channel between remote host and CNXK SoC over PCIe. +#. Transfer packets received from network interface to remote host over PCIe and + vice-versa. + +CNXK packet flow +---------------------- + +The :numref:`figure_cnxk_packet_flow_hw_accelerators` diagram depicts +the packet flow on CNXK SoC in conjunction with use of various HW accelerators. + +.. _figure_cnxk_packet_flow_hw_accelerators: + +.. figure:: img/cnxk_packet_flow_hw_accelerators.* + + CNXK packet flow in conjunction with use of HW accelerators + +HW Offload Drivers +------------------ + +This section lists dataplane H/W block(s) available in CNXK SoC. + +Procedure to Setup Platform +--------------------------- + +There are three main prerequisites for setting up DPDK on CNXK +compatible board: + +1. **RVU AF Linux kernel driver** + + The dependent kernel drivers can be obtained from the + `kernel.org `_. + + Alternatively, the Marvell SDK also provides the required kernel drivers. + + Linux kernel should be configured with the following features enabled: + +.. code-block:: console + + # 64K pages enabled for better performance + CONFIG_ARM64_64K_PAGES=y + CONFIG_ARM64_VA_BITS_48=y + # huge pages support enabled + CONFIG_HUGETLBFS=y + CONFIG_HUGETLB_PAGE=y + # VFIO enabled with TYPE1 IOMMU at minimum + CONFIG_VFIO_IOMMU_TYPE1=y + CONFIG_VFIO_VIRQFD=y + CONFIG_VFIO=y + CONFIG_VFIO_NOIOMMU=y + CONFIG_VFIO_PCI=y + CONFIG_VFIO_PCI_MMAP=y + # SMMUv3 driver + CONFIG_ARM_SMMU_V3=y + # ARMv8.1 LSE atomics + CONFIG_ARM64_LSE_ATOMICS=y + # OCTEONTX2 drivers + CONFIG_OCTEONTX2_MBOX=y + CONFIG_OCTEONTX2_AF=y + # Enable if netdev PF driver required + CONFIG_OCTEONTX2_PF=y + # Enable if netdev VF driver required + CONFIG_OCTEONTX2_VF=y + CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y + # Enable if OCTEONTX2 DMA PF driver required + CONFIG_OCTEONTX2_DPI_PF=n + +2. **ARM64 Linux Tool Chain** + + For example, the *aarch64* Linaro Toolchain, which can be obtained from + `here `_. + + Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is + optimized for CNXK CPU. + +3. **Rootfile system** + + Any *aarch64* supporting filesystem may be used. For example, + Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained + from ``_. + + Alternatively, the Marvell SDK provides the buildroot based root filesystem. + The SDK includes all the above prerequisites necessary to bring up the CNXK board. + +- Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment. + + +Debugging Options +----------------- + +.. _table_cnxk_common_debug_options: + +.. table:: CNXK common debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | Common | --log-level='pmd\.cnxk\.base,8' | + +---+------------+-------------------------------------------------------+ + | 2 | Mailbox | --log-level='pmd\.cnxk\.mbox,8' | + +---+------------+-------------------------------------------------------+ + +Debugfs support +~~~~~~~~~~~~~~~ + +The **RVU AF Linux kernel driver** provides support to dump RVU blocks +context or stats using debugfs. + +Enable ``debugfs`` by: + +1. Compile kernel with debugfs enabled, i.e ``CONFIG_DEBUGFS=y``. +2. Boot OCTEON CN9K/CN10K with debugfs supported kernel. +3. Verify ``debugfs`` mounted by default "mount | grep -i debugfs" or mount it manually by using. + +.. code-block:: console + + # mount -t debugfs none /sys/kernel/debug + +Currently ``debugfs`` supports the following RVU blocks NIX, NPA, NPC, NDC, +SSO & RPM. + +The file structure under ``/sys/kernel/debug`` is as follows + +.. code-block:: console + + octeontx2/ + | + cn10k/ + |-- rpm + | |-- rpm0 + | | '-- lmac0 + | | '-- stats + | |-- rpm1 + | | |-- lmac0 + | | | '-- stats + | | '-- lmac1 + | | '-- stats + | '-- rpm2 + | '-- lmac0 + | '-- stats + |-- cpt + | |-- cpt_engines_info + | |-- cpt_engines_sts + | |-- cpt_err_info + | |-- cpt_lfs_info + | '-- cpt_pc + |---- nix + | |-- cq_ctx + | |-- ndc_rx_cache + | |-- ndc_rx_hits_miss + | |-- ndc_tx_cache + | |-- ndc_tx_hits_miss + | |-- qsize + | |-- rq_ctx + | '-- sq_ctx + |-- npa + | |-- aura_ctx + | |-- ndc_cache + | |-- ndc_hits_miss + | |-- pool_ctx + | '-- qsize + |-- npc + | |-- mcam_info + | |-- mcam_rules + | '-- rx_miss_act_stats + |-- rsrc_alloc + '-- sso + |-- hws + | '-- sso_hws_info + '-- hwgrp + |-- sso_hwgrp_aq_thresh + |-- sso_hwgrp_iaq_walk + |-- sso_hwgrp_pc + |-- sso_hwgrp_free_list_walk + |-- sso_hwgrp_ient_walk + '-- sso_hwgrp_taq_walk + +RVU block LF allocation: + +.. code-block:: console + + cat /sys/kernel/debug/cn10k/rsrc_alloc + + pcifunc NPA NIX SSO GROUP SSOWS TIM CPT + PF1 0 0 + PF4 1 + PF13 0, 1 0, 1 0 + +RPM example usage: + +.. code-block:: console + + cat /sys/kernel/debug/cn10k/rpm/rpm0/lmac0/stats + + =======Link Status====== + + Link is UP 25000 Mbps + + =======NIX RX_STATS(rpm port level)====== + + rx_ucast_frames: 0 + rx_mcast_frames: 0 + rx_bcast_frames: 0 + rx_frames: 0 + rx_bytes: 0 + rx_drops: 0 + rx_errors: 0 + + =======NIX TX_STATS(rpm port level)====== + + tx_ucast_frames: 0 + tx_mcast_frames: 0 + tx_bcast_frames: 0 + tx_frames: 0 + tx_bytes: 0 + tx_drops: 0 + + =======rpm RX_STATS====== + + Octets of received packets: 0 + Octets of received packets with out error: 0 + Received packets with alignment errors: 0 + Control/PAUSE packets received: 0 + Packets received with Frame too long Errors: 0 + Packets received with a1nrange length Errors: 0 + Received packets: 0 + Packets received with FrameCheckSequenceErrors: 0 + Packets received with VLAN header: 0 + Error packets: 0 + Packets recievd with unicast DMAC: 0 + Packets received with multicast DMAC: 0 + Packets received with broadcast DMAC: 0 + Dropped packets: 0 + Total frames received on interface: 0 + Packets received with an octet count < 64: 0 + Packets received with an octet count == 64: 0 + Packets received with an octet count of 65–127: 0 + Packets received with an octet count of 128-255: 0 + Packets received with an octet count of 256-511: 0 + Packets received with an octet count of 512-1023: 0 + Packets received with an octet count of 1024-1518: 0 + Packets received with an octet count of > 1518: 0 + Oversized Packets: 0 + Jabber Packets: 0 + Fragmented Packets: 0 + CBFC(class based flow control) pause frames received for class 0: 0 + CBFC pause frames received for class 1: 0 + CBFC pause frames received for class 2: 0 + CBFC pause frames received for class 3: 0 + CBFC pause frames received for class 4: 0 + CBFC pause frames received for class 5: 0 + CBFC pause frames received for class 6: 0 + CBFC pause frames received for class 7: 0 + CBFC pause frames received for class 8: 0 + CBFC pause frames received for class 9: 0 + CBFC pause frames received for class 10: 0 + CBFC pause frames received for class 11: 0 + CBFC pause frames received for class 12: 0 + CBFC pause frames received for class 13: 0 + CBFC pause frames received for class 14: 0 + CBFC pause frames received for class 15: 0 + MAC control packets received: 0 + + =======rpm TX_STATS====== + + Total octets sent on the interface: 0 + Total octets transmitted OK: 0 + Control/Pause frames sent: 0 + Total frames transmitted OK: 0 + Total frames sent with VLAN header: 0 + Error Packets: 0 + Packets sent to to unicast DMAC: 0 + Packets sent to the multicast DMAC: 0 + Packets sent to a broadcast DMAC: 0 + Packets sent with an octet count == 64: 0 + Packets sent with an octet count of 65–127: 0 + Packets sent with an octet count of 128-255: 0 + Packets sent with an octet count of 256-511: 0 + Packets sent with an octet count of 512-1023: 0 + Packets sent with an octet count of 1024-1518: 0 + Packets sent with an octet count of > 1518: 0 + CBFC(class based flow control) pause frames transmitted for class 0: 0 + CBFC pause frames transmitted for class 1: 0 + CBFC pause frames transmitted for class 2: 0 + CBFC pause frames transmitted for class 3: 0 + CBFC pause frames transmitted for class 4: 0 + CBFC pause frames transmitted for class 5: 0 + CBFC pause frames transmitted for class 6: 0 + CBFC pause frames transmitted for class 7: 0 + CBFC pause frames transmitted for class 8: 0 + CBFC pause frames transmitted for class 9: 0 + CBFC pause frames transmitted for class 10: 0 + CBFC pause frames transmitted for class 11: 0 + CBFC pause frames transmitted for class 12: 0 + CBFC pause frames transmitted for class 13: 0 + CBFC pause frames transmitted for class 14: 0 + CBFC pause frames transmitted for class 15: 0 + MAC control packets sent: 0 + Total frames sent on the interface: 0 + +CPT example usage: + +.. code-block:: console + + cat /sys/kernel/debug/cn10k/cpt/cpt_pc + + CPT instruction requests 0 + CPT instruction latency 0 + CPT NCB read requests 0 + CPT NCB read latency 0 + CPT read requests caused by UC fills 0 + CPT active cycles pc 1395642 + CPT clock count pc 5579867595493 + +NIX example usage: + +.. code-block:: console + + Usage: echo [cq number/all] > /sys/kernel/debug/cn10k/nix/cq_ctx + cat /sys/kernel/debug/cn10k/nix/cq_ctx + echo 0 0 > /sys/kernel/debug/cn10k/nix/cq_ctx + cat /sys/kernel/debug/cn10k/nix/cq_ctx + + =====cq_ctx for nixlf:0 and qidx:0 is===== + W0: base 158ef1a00 + + W1: wrptr 0 + W1: avg_con 0 + W1: cint_idx 0 + W1: cq_err 0 + W1: qint_idx 0 + W1: bpid 0 + W1: bp_ena 0 + + W2: update_time 31043 + W2:avg_level 255 + W2: head 0 + W2:tail 0 + + W3: cq_err_int_ena 5 + W3:cq_err_int 0 + W3: qsize 4 + W3:caching 1 + W3: substream 0x000 + W3: ena 1 + W3: drop_ena 1 + W3: drop 64 + W3: bp 0 + +NPA example usage: + +.. code-block:: console + + Usage: echo [pool number/all] > /sys/kernel/debug/cn10k/npa/pool_ctx + cat /sys/kernel/debug/cn10k/npa/pool_ctx + echo 0 0 > /sys/kernel/debug/cn10k/npa/pool_ctx + cat /sys/kernel/debug/cn10k/npa/pool_ctx + + ======POOL : 0======= + W0: Stack base 1375bff00 + W1: ena 1 + W1: nat_align 1 + W1: stack_caching 1 + W1: stack_way_mask 0 + W1: buf_offset 1 + W1: buf_size 19 + W2: stack_max_pages 24315 + W2: stack_pages 24314 + W3: op_pc 267456 + W4: stack_offset 2 + W4: shift 5 + W4: avg_level 255 + W4: avg_con 0 + W4: fc_ena 0 + W4: fc_stype 0 + W4: fc_hyst_bits 0 + W4: fc_up_crossing 0 + W4: update_time 62993 + W5: fc_addr 0 + W6: ptr_start 1593adf00 + W7: ptr_end 180000000 + W8: err_int 0 + W8: err_int_ena 7 + W8: thresh_int 0 + W8: thresh_int_ena 0 + W8: thresh_up 0 + W8: thresh_qint_idx 0 + W8: err_qint_idx 0 + +NPC example usage: + +.. code-block:: console + + cat /sys/kernel/debug/cn10k/npc/mcam_info + + NPC MCAM info: + RX keywidth : 224bits + TX keywidth : 224bits + + MCAM entries : 2048 + Reserved : 158 + Available : 1890 + + MCAM counters : 512 + Reserved : 1 + Available : 511 + +SSO example usage: + +.. code-block:: console + + Usage: echo [/all] > /sys/kernel/debug/cn10k/sso/hws/sso_hws_info + echo 0 > /sys/kernel/debug/cn10k/sso/hws/sso_hws_info + + ================================================== + SSOW HWS[0] Arbitration State 0x0 + SSOW HWS[0] Guest Machine Control 0x0 + SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff + SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff + SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff + SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff + SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff + SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff + SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff + SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff + ================================================== + +Compile DPDK +------------ + +DPDK may be compiled either natively on OCTEON CN9K/CN10K platform or cross-compiled on +an x86 based platform. + +Native Compilation +~~~~~~~~~~~~~~~~~~ + +.. code-block:: console + + meson build + ninja -C build + +Cross Compilation +~~~~~~~~~~~~~~~~~ + +Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details. + +.. code-block:: console + + meson build --cross-file config/arm/arm64_cn10k_linux_gcc + ninja -C build + +.. note:: + + By default, meson cross compilation uses ``aarch64-linux-gnu-gcc`` toolchain, + if Marvell toolchain is available then it can be used by overriding the + c, cpp, ar, strip ``binaries`` attributes to respective Marvell + toolchain binaries in ``config/arm/arm64_cn10k_linux_gcc`` file. diff --git a/doc/guides/platform/img/cnxk_packet_flow_hw_accelerators.svg b/doc/guides/platform/img/cnxk_packet_flow_hw_accelerators.svg new file mode 100644 index 0000000..6d4a492 --- /dev/null +++ b/doc/guides/platform/img/cnxk_packet_flow_hw_accelerators.svg @@ -0,0 +1,2795 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + DDDpk + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx Rx + HW loop back device + + + + + + + + + + + + + + + + + Ethdev Ports (NIX) + Ingress Classification(NPC) + Egress Classification(NPC) + Rx Queues + Tx Queues + EgressTraffic Manager(NIX) + Scheduler SSO + Supports both poll mode and/or event modeby configuring scheduler + ARMv8/v9Cores + Hardware Libraries + Software Libraries + Mempool(NPA) + Timer(TIM) + Crypto(CPT) + Compress(ZIP) + SharedMemory + SW Ring + HASHLPMACL + Mbuf + De(Frag) + + diff --git a/doc/guides/platform/img/cnxk_resource_virtualization.svg b/doc/guides/platform/img/cnxk_resource_virtualization.svg new file mode 100644 index 0000000..ec89bb7 --- /dev/null +++ b/doc/guides/platform/img/cnxk_resource_virtualization.svg @@ -0,0 +1,2428 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + +   + + + + + + + + + + NIX AF + NPA AF + SSO AF + NPC AF + CPT AF + RVU AF + Linux AF driver(octeontx2_af)PF0 + + + CGX/RPM-0 + + + + CGX/RPM-1 + + + + + CGX/RPM-2 + + CGX/RPM-FW Iface + + + + + + + + + AF-PF MBOX + Linux Netdev PFdriver(octeontx2_pf)PFx + + NIX LF + + NPA LF + + + PF-VF MBOX + CGX/RPM-x LMAC-y + + + + + + + + Linux Netdev VFdriver(octeontx2_vf)PFx-VF0 + + NIX LF + + NPA LF + DPDK Ethdev VFdriverPFx-VF1 + + NIX LF + + NPA LF + + + DPDK Ethdev PFdriverPFy + + NIX LF + + NPA LF + PF-VF MBOX + + DPDK Eventdev PFdriverPFz + + TIM LF + + SSO LF + Linux Crypto PFdriverPFm + + NIX LF + + NPA LF + DPDK Ethdev VFdriverPFy-VF0 + + CPT LF + DPDK Crypto VFdriverPFm-VF0 + PF-VF MBOX + + DDDpk DPDK-APP1 with one ethdev over Linux PF + + DPDK-APP2 with Two ethdevs(PF,VF) ,eventdev, timer adapter and cryptodev + + + + + CGX/RPM-x LMAC-y + + + diff --git a/doc/guides/platform/index.rst b/doc/guides/platform/index.rst index f454ef8..7614e1a 100644 --- a/doc/guides/platform/index.rst +++ b/doc/guides/platform/index.rst @@ -11,6 +11,7 @@ The following are platform specific guides and setup information. :numbered: bluefield + cnxk dpaa dpaa2 octeontx -- 2.8.4