From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44AB2A0548; Thu, 1 Apr 2021 12:03:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A39C140EE9; Thu, 1 Apr 2021 12:03:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 389A3140EBD for ; Thu, 1 Apr 2021 12:03:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 131A12eU009418; Thu, 1 Apr 2021 03:03:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=I05IG6QQQ8tsmDTTCyKuXQcx9vONI28P2I+xYWWdt9Q=; b=RhPyaXTS43imBIqPyvJIL9skj8NMjsRzYUMkC6bSDc2ZqfNq2+xHO6cLxy/ZJ8Iyz5+y qQF1rcwpvQRt/StT+FjXg7feasT+cWlZf7vJPA4iu49icCkNosYw6aR8+sykhmrwNlZs DYrt/Fa+jsi+FybN6n2nLhn4hZ+ghrkEjHHqVIlyGoCqodI8+SI/rr4jUv+3P/gvkD97 v0miHVb9XcR7+McEDKeH4sWrLgajyQObrVNcMngiPtTuwcNiSbCA/dMPphH6rtN9jgBw Ops4m8UedNvO5VLXdmNnnzvEZFBwYEU9CVCV7p1OlgS8p8JcaRHjai1VLeELRgg3L2Xv 9A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37n28jhya2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 01 Apr 2021 03:03:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 03:03:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 03:03:28 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0BFE93F703F; Thu, 1 Apr 2021 03:03:23 -0700 (PDT) From: Nithin Dabilpuram To: , Jan Viktorin , Ruifeng Wang , Honnappa Nagarahalli CC: , , , , , , , Nithin Dabilpuram Date: Thu, 1 Apr 2021 15:33:12 +0530 Message-ID: <20210401100312.27436-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210331172320.29130-1-ndabilpuram@marvell.com> References: <20210331172320.29130-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: M1ITRBK6ucdJi1gb5ao50cPhTD2rFvuv X-Proofpoint-ORIG-GUID: M1ITRBK6ucdJi1gb5ao50cPhTD2rFvuv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_04:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v2] config/arm: add support for Marvell CN10K X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add config support to cross compile for Marvell CN10K SoC. Marvell CN10K SoC is based on ARM Neoverse N2 core. Signed-off-by: Nithin Dabilpuram Signed-off-by: Pavan Nikhilesh Acked-by: Jerin Jacob --- v2: - Fix commit message. config/arm/arm64_cn10k_linux_gcc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 config/arm/arm64_cn10k_linux_gcc diff --git a/config/arm/arm64_cn10k_linux_gcc b/config/arm/arm64_cn10k_linux_gcc new file mode 100644 index 0000000..4f8e7cb --- /dev/null +++ b/config/arm/arm64_cn10k_linux_gcc @@ -0,0 +1,20 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pkgconfig = 'aarch64-linux-gnu-pkg-config' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8.6-a' +endian = 'little' + +[properties] +implementer_id = '0x41' +part_number = '0xd49' +max_lcores = 36 +max_numa_nodes = 1 +numa = false -- 2.8.4