From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 178E1A0548; Sat, 3 Apr 2021 16:19:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F342F140E1B; Sat, 3 Apr 2021 16:18:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4F3A9140E6C for ; Sat, 3 Apr 2021 16:18:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 133EHL4f003697 for ; Sat, 3 Apr 2021 07:18:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=sgMBQhfl7FE1PTIvm1+6MzzQfeIN1WWnJsnQNX1UOPQ=; b=ZzMFwVxuPQYpkw6F97SVVkTZZw/HpFP2eIBIpR69ByMP1NYf3rn0sGottUoQX0nZz3ml Z+mP4IyUacJT8rVrxAiO/u74q0TGrQy2dmFXuVH48mGhRD/2WOTZxuJ6dQlKEtKfhGnX 8knc5Z4hrMJsyp1e4n3oVHLHZkyHARbSH3nnrchF0sh4ZxHcWO5jiHIPR5PxQJ4pPZv7 QbbafNOlR5+pEADZtgxlvKXuPvBlUGkYX7F5O+Bje2C/XfTgNJKAMYyoX9ojGY5K7j+1 qiDLWwQFOaxJMv8dSXb+oKQegNCZW46aohXWnYwawwk1Xq1N3D80yLoZZIdZLJpawxYa AQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37pqvt86ep-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 03 Apr 2021 07:18:40 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 3 Apr 2021 07:18:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 3 Apr 2021 07:18:38 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 927F53F7040; Sat, 3 Apr 2021 07:18:35 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Sat, 3 Apr 2021 19:47:49 +0530 Message-ID: <20210403141751.215926-9-asekhar@marvell.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210403141751.215926-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> <20210403141751.215926-1-asekhar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: QyjyHeJT_LigojxV-MFD4Z41QEXKeuLW X-Proofpoint-ORIG-GUID: QyjyHeJT_LigojxV-MFD4Z41QEXKeuLW X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-03_05:2021-04-01, 2021-04-03 signatures=0 Subject: [dpdk-dev] [PATCH v2 09/11] mempool/cnxk: add cn10k batch enqueue op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the implementation for Marvell CN10k mempool batch enqueue op. Signed-off-by: Ashwin Sekhar T K --- drivers/mempool/cnxk/cn10k_mempool_ops.c | 28 +++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index d34041528a..2e3ec414da 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -112,6 +112,32 @@ batch_op_fini(struct rte_mempool *mp) BATCH_OP_DATA_SET(mp->pool_id, NULL); } +static int __rte_hot +cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, + unsigned int n) +{ + const uint64_t *ptr = (const uint64_t *)obj_table; + uint64_t lmt_addr = 0, lmt_id = 0; + struct batch_op_data *op_data; + + /* Ensure mbuf init changes are written before the free pointers are + * enqueued to the stack. + */ + rte_io_wmb(); + + if (n == 1) { + roc_npa_aura_op_free(mp->pool_id, 1, ptr[0]); + return 0; + } + + op_data = BATCH_OP_DATA_GET(mp->pool_id); + lmt_addr = op_data->lmt_addr; + ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id); + roc_npa_aura_op_batch_free(mp->pool_id, ptr, n, 1, lmt_addr, lmt_id); + + return 0; +} + static int cn10k_mempool_alloc(struct rte_mempool *mp) { @@ -162,7 +188,7 @@ static struct rte_mempool_ops cn10k_mempool_ops = { .name = "cn10k_mempool_ops", .alloc = cn10k_mempool_alloc, .free = cn10k_mempool_free, - .enqueue = cnxk_mempool_enq, + .enqueue = cn10k_mempool_enq, .dequeue = cnxk_mempool_deq, .get_count = cnxk_mempool_get_count, .calc_mem_size = cnxk_mempool_calc_mem_size, -- 2.31.0