From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FABFA0546; Tue, 6 Apr 2021 16:46:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA5C5141052; Tue, 6 Apr 2021 16:43:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 457CA141052 for ; Tue, 6 Apr 2021 16:43:12 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 136EebZN005021 for ; Tue, 6 Apr 2021 07:43:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=xkkjCLZEh87qn0ZyemD00JcK5KikziasvGAk6p3P5ew=; b=eiFB6Dm1wffhebvZBZVukbeXbW8rOdyfKs3+78kN0y4pUFC8a/E9odVNJtOGvMrLoKmd T3NGwhb16eZG20VWejY2vmMxLWRpTVBknJQsqKEGD3UgH7M1/UxiysfOPmS+gtZS2kz5 Vxku/kjsrwRsXNoSPNBXDGDfaNFvAJp+f1t+ucZp210iaSo3Tblj3JOi8cJgnf21hKm/ +aHgsYvxrP8ylh/s2T0prDlSoMJAHxKnhoAgnHsWQc9wkTWM4Mv9wM90SPTr8kkogv4x OpuQAoZIhc10b9NwWVdYjYEZtoCr7Ke4JBe6QaLybkDYMsihyHrmi4rY1XvtAoi23Tbs DA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37redm9wkj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Apr 2021 07:43:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 07:43:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Apr 2021 07:43:09 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 2D7CF3F7041; Tue, 6 Apr 2021 07:43:06 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Tue, 6 Apr 2021 20:11:18 +0530 Message-ID: <20210406144144.19925-27-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210406144144.19925-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210406144144.19925-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: lk_QKstCQetcwSyyk8RrEfeWQhDJhPh0 X-Proofpoint-ORIG-GUID: lk_QKstCQetcwSyyk8RrEfeWQhDJhPh0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-06_03:2021-04-01, 2021-04-06 signatures=0 Subject: [dpdk-dev] [PATCH v5 26/52] common/cnxk: add nix stats support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add API to provide Rx and Tx stats for a given NIX. Signed-off-by: Jerin Jacob --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_nix.h | 53 ++++++++ drivers/common/cnxk/roc_nix_stats.c | 239 ++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 4 + 4 files changed, 297 insertions(+) create mode 100644 drivers/common/cnxk/roc_nix_stats.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index d01cf0b..4c48f55 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -23,6 +23,7 @@ sources = files('roc_dev.c', 'roc_nix_ptp.c', 'roc_nix_queue.c', 'roc_nix_rss.c', + 'roc_nix_stats.c', 'roc_npa.c', 'roc_npa_debug.c', 'roc_npa_irq.c', diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 3cc1797..45aca83 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -47,6 +47,49 @@ enum roc_nix_sq_max_sqe_sz { #define ROC_NIX_VWQE_MAX_SIZE_LOG2 11 #define ROC_NIX_VWQE_MIN_SIZE_LOG2 2 +struct roc_nix_stats { + /* Rx */ + uint64_t rx_octs; + uint64_t rx_ucast; + uint64_t rx_bcast; + uint64_t rx_mcast; + uint64_t rx_drop; + uint64_t rx_drop_octs; + uint64_t rx_fcs; + uint64_t rx_err; + uint64_t rx_drop_bcast; + uint64_t rx_drop_mcast; + uint64_t rx_drop_l3_bcast; + uint64_t rx_drop_l3_mcast; + /* Tx */ + uint64_t tx_ucast; + uint64_t tx_bcast; + uint64_t tx_mcast; + uint64_t tx_drop; + uint64_t tx_octs; +}; + +struct roc_nix_stats_queue { + PLT_STD_C11 + union { + struct { + /* Rx */ + uint64_t rx_pkts; + uint64_t rx_octs; + uint64_t rx_drop_pkts; + uint64_t rx_drop_octs; + uint64_t rx_error_pkts; + }; + struct { + /* Tx */ + uint64_t tx_pkts; + uint64_t tx_octs; + uint64_t tx_drop_pkts; + uint64_t tx_drop_octs; + }; + }; +}; + struct roc_nix_rq { /* Input parameters */ uint16_t qid; @@ -237,6 +280,16 @@ int __roc_api roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx, int __roc_api roc_nix_rss_default_setup(struct roc_nix *roc_nix, uint32_t flowkey); +/* Stats */ +int __roc_api roc_nix_stats_get(struct roc_nix *roc_nix, + struct roc_nix_stats *stats); +int __roc_api roc_nix_stats_reset(struct roc_nix *roc_nix); +int __roc_api roc_nix_stats_queue_get(struct roc_nix *roc_nix, uint16_t qid, + bool is_rx, + struct roc_nix_stats_queue *qstats); +int __roc_api roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid, + bool is_rx); + /* Queue */ int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena); diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c new file mode 100644 index 0000000..e0a776a --- /dev/null +++ b/drivers/common/cnxk/roc_nix_stats.c @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include + +#include "roc_api.h" +#include "roc_priv.h" + +#define NIX_RX_STATS(val) plt_read64(nix->base + NIX_LF_RX_STATX(val)) +#define NIX_TX_STATS(val) plt_read64(nix->base + NIX_LF_TX_STATX(val)) + +int +roc_nix_stats_get(struct roc_nix *roc_nix, struct roc_nix_stats *stats) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + if (stats == NULL) + return NIX_ERR_PARAM; + + stats->rx_octs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_OCTS); + stats->rx_ucast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_UCAST); + stats->rx_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_BCAST); + stats->rx_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_MCAST); + stats->rx_drop = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DROP); + stats->rx_drop_octs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DROP_OCTS); + stats->rx_fcs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_FCS); + stats->rx_err = NIX_RX_STATS(NIX_STAT_LF_RX_RX_ERR); + stats->rx_drop_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_BCAST); + stats->rx_drop_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_MCAST); + stats->rx_drop_l3_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_L3BCAST); + stats->rx_drop_l3_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_L3MCAST); + + stats->tx_ucast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_UCAST); + stats->tx_bcast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_BCAST); + stats->tx_mcast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_MCAST); + stats->tx_drop = NIX_TX_STATS(NIX_STAT_LF_TX_TX_DROP); + stats->tx_octs = NIX_TX_STATS(NIX_STAT_LF_TX_TX_OCTS); + return 0; +} + +int +roc_nix_stats_reset(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = (&nix->dev)->mbox; + + if (mbox_alloc_msg_nix_stats_rst(mbox) == NULL) + return -ENOMEM; + + return mbox_process(mbox); +} + +static int +queue_is_valid(struct nix *nix, uint16_t qid, bool is_rx) +{ + uint16_t nb_queues; + + if (is_rx) + nb_queues = nix->nb_rx_queues; + else + nb_queues = nix->nb_tx_queues; + + if (qid >= nb_queues) + return NIX_ERR_QUEUE_INVALID_RANGE; + + return 0; +} + +static uint64_t +qstat_read(struct nix *nix, uint16_t qid, uint32_t off) +{ + uint64_t reg, val; + int64_t *addr; + + addr = (int64_t *)(nix->base + off); + reg = (((uint64_t)qid) << 32); + val = roc_atomic64_add_nosync(reg, addr); + if (val & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR)) + val = 0; + return val; +} + +static void +nix_stat_rx_queue_get(struct nix *nix, uint16_t qid, + struct roc_nix_stats_queue *qstats) +{ + qstats->rx_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_PKTS); + qstats->rx_octs = qstat_read(nix, qid, NIX_LF_RQ_OP_OCTS); + qstats->rx_drop_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_DROP_PKTS); + qstats->rx_drop_octs = qstat_read(nix, qid, NIX_LF_RQ_OP_DROP_OCTS); + qstats->rx_error_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_RE_PKTS); +} + +static void +nix_stat_tx_queue_get(struct nix *nix, uint16_t qid, + struct roc_nix_stats_queue *qstats) +{ + qstats->tx_pkts = qstat_read(nix, qid, NIX_LF_SQ_OP_PKTS); + qstats->tx_octs = qstat_read(nix, qid, NIX_LF_SQ_OP_OCTS); + qstats->tx_drop_pkts = qstat_read(nix, qid, NIX_LF_SQ_OP_DROP_PKTS); + qstats->tx_drop_octs = qstat_read(nix, qid, NIX_LF_SQ_OP_DROP_OCTS); +} + +static int +nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid) +{ + struct mbox *mbox = (&nix->dev)->mbox; + int rc; + + if (roc_model_is_cn9k()) { + struct nix_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_aq_enq(mbox); + aq->qidx = qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->rq.octs = 0; + aq->rq.pkts = 0; + aq->rq.drop_octs = 0; + aq->rq.drop_pkts = 0; + aq->rq.re_pkts = 0; + + aq->rq_mask.octs = ~(aq->rq_mask.octs); + aq->rq_mask.pkts = ~(aq->rq_mask.pkts); + aq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs); + aq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts); + aq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts); + } else { + struct nix_cn10k_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + aq->qidx = qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->rq.octs = 0; + aq->rq.pkts = 0; + aq->rq.drop_octs = 0; + aq->rq.drop_pkts = 0; + aq->rq.re_pkts = 0; + + aq->rq_mask.octs = ~(aq->rq_mask.octs); + aq->rq_mask.pkts = ~(aq->rq_mask.pkts); + aq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs); + aq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts); + aq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts); + } + + rc = mbox_process(mbox); + return rc ? NIX_ERR_AQ_WRITE_FAILED : 0; +} + +static int +nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid) +{ + struct mbox *mbox = (&nix->dev)->mbox; + int rc; + + if (roc_model_is_cn9k()) { + struct nix_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_aq_enq(mbox); + aq->qidx = qid; + aq->ctype = NIX_AQ_CTYPE_SQ; + aq->op = NIX_AQ_INSTOP_WRITE; + aq->sq.octs = 0; + aq->sq.pkts = 0; + aq->sq.drop_octs = 0; + aq->sq.drop_pkts = 0; + + aq->sq_mask.octs = ~(aq->sq_mask.octs); + aq->sq_mask.pkts = ~(aq->sq_mask.pkts); + aq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs); + aq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts); + } else { + struct nix_cn10k_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + aq->qidx = qid; + aq->ctype = NIX_AQ_CTYPE_SQ; + aq->op = NIX_AQ_INSTOP_WRITE; + aq->sq.octs = 0; + aq->sq.pkts = 0; + aq->sq.drop_octs = 0; + aq->sq.drop_pkts = 0; + + aq->sq_mask.octs = ~(aq->sq_mask.octs); + aq->sq_mask.pkts = ~(aq->sq_mask.pkts); + aq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs); + aq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts); + } + + rc = mbox_process(mbox); + return rc ? NIX_ERR_AQ_WRITE_FAILED : 0; +} + +int +roc_nix_stats_queue_get(struct roc_nix *roc_nix, uint16_t qid, bool is_rx, + struct roc_nix_stats_queue *qstats) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int rc; + + if (qstats == NULL) + return NIX_ERR_PARAM; + + rc = queue_is_valid(nix, qid, is_rx); + if (rc) + goto fail; + + if (is_rx) + nix_stat_rx_queue_get(nix, qid, qstats); + else + nix_stat_tx_queue_get(nix, qid, qstats); + +fail: + return rc; +} + +int +roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid, bool is_rx) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int rc; + + rc = queue_is_valid(nix, qid, is_rx); + if (rc) + goto fail; + + if (is_rx) + rc = nix_stat_rx_queue_reset(nix, qid); + else + rc = nix_stat_tx_queue_reset(nix, qid); + +fail: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 2267cf7..2ff3065 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -79,6 +79,10 @@ INTERNAL { roc_nix_rx_queue_intr_enable; roc_nix_sq_fini; roc_nix_sq_init; + roc_nix_stats_get; + roc_nix_stats_queue_get; + roc_nix_stats_queue_reset; + roc_nix_stats_reset; roc_nix_unregister_cq_irqs; roc_nix_unregister_queue_irqs; roc_npa_aura_limit_modify; -- 2.8.4