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From: Ashwin Sekhar T K <asekhar@marvell.com>
To: <dev@dpdk.org>
Cc: <jerinj@marvell.com>, <skori@marvell.com>,
	<skoteshwar@marvell.com>, <pbhagavatula@marvell.com>,
	<kirankumark@marvell.com>, <psatheesh@marvell.com>,
	<asekhar@marvell.com>
Subject: [dpdk-dev] [PATCH v4 03/11] mempool/cnxk: add generic ops
Date: Thu, 8 Apr 2021 15:20:41 +0530
Message-ID: <20210408095049.3100322-4-asekhar@marvell.com> (raw)
In-Reply-To: <20210408095049.3100322-1-asekhar@marvell.com>

Add generic CNXk mempool ops which will enqueue/dequeue
from pool one element at a time.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
 drivers/mempool/cnxk/cnxk_mempool.h     |  26 ++++
 drivers/mempool/cnxk/cnxk_mempool_ops.c | 171 ++++++++++++++++++++++++
 drivers/mempool/cnxk/meson.build        |   3 +-
 3 files changed, 199 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mempool/cnxk/cnxk_mempool.h
 create mode 100644 drivers/mempool/cnxk/cnxk_mempool_ops.c

diff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h
new file mode 100644
index 0000000000..099b7f6998
--- /dev/null
+++ b/drivers/mempool/cnxk/cnxk_mempool.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_MEMPOOL_H_
+#define _CNXK_MEMPOOL_H_
+
+#include <rte_mempool.h>
+
+unsigned int cnxk_mempool_get_count(const struct rte_mempool *mp);
+ssize_t cnxk_mempool_calc_mem_size(const struct rte_mempool *mp,
+				   uint32_t obj_num, uint32_t pg_shift,
+				   size_t *min_chunk_size, size_t *align);
+int cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs,
+			  void *vaddr, rte_iova_t iova, size_t len,
+			  rte_mempool_populate_obj_cb_t *obj_cb,
+			  void *obj_cb_arg);
+int cnxk_mempool_alloc(struct rte_mempool *mp);
+void cnxk_mempool_free(struct rte_mempool *mp);
+
+int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table,
+			       unsigned int n);
+int __rte_hot cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table,
+			       unsigned int n);
+
+#endif
diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c
new file mode 100644
index 0000000000..2ce1816c04
--- /dev/null
+++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_mempool.h>
+
+#include "roc_api.h"
+#include "cnxk_mempool.h"
+
+int __rte_hot
+cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n)
+{
+	unsigned int index;
+
+	/* Ensure mbuf init changes are written before the free pointers
+	 * are enqueued to the stack.
+	 */
+	rte_io_wmb();
+	for (index = 0; index < n; index++)
+		roc_npa_aura_op_free(mp->pool_id, 0,
+				     (uint64_t)obj_table[index]);
+
+	return 0;
+}
+
+int __rte_hot
+cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)
+{
+	unsigned int index;
+	uint64_t obj;
+
+	for (index = 0; index < n; index++, obj_table++) {
+		int retry = 4;
+
+		/* Retry few times before failing */
+		do {
+			obj = roc_npa_aura_op_alloc(mp->pool_id, 0);
+		} while (retry-- && (obj == 0));
+
+		if (obj == 0) {
+			cnxk_mempool_enq(mp, obj_table - index, index);
+			return -ENOENT;
+		}
+		*obj_table = (void *)obj;
+	}
+
+	return 0;
+}
+
+unsigned int
+cnxk_mempool_get_count(const struct rte_mempool *mp)
+{
+	return (unsigned int)roc_npa_aura_op_available(mp->pool_id);
+}
+
+ssize_t
+cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num,
+			   uint32_t pg_shift, size_t *min_chunk_size,
+			   size_t *align)
+{
+	size_t total_elt_sz;
+
+	/* Need space for one more obj on each chunk to fulfill
+	 * alignment requirements.
+	 */
+	total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
+	return rte_mempool_op_calc_mem_size_helper(
+		mp, obj_num, pg_shift, total_elt_sz, min_chunk_size, align);
+}
+
+int
+cnxk_mempool_alloc(struct rte_mempool *mp)
+{
+	uint64_t aura_handle = 0;
+	struct npa_aura_s aura;
+	struct npa_pool_s pool;
+	uint32_t block_count;
+	size_t block_size;
+	int rc = -ERANGE;
+
+	block_size = mp->elt_size + mp->header_size + mp->trailer_size;
+	block_count = mp->size;
+	if (mp->header_size % ROC_ALIGN != 0) {
+		plt_err("Header size should be multiple of %dB", ROC_ALIGN);
+		goto error;
+	}
+
+	if (block_size % ROC_ALIGN != 0) {
+		plt_err("Block size should be multiple of %dB", ROC_ALIGN);
+		goto error;
+	}
+
+	memset(&aura, 0, sizeof(struct npa_aura_s));
+	memset(&pool, 0, sizeof(struct npa_pool_s));
+	pool.nat_align = 1;
+	pool.buf_offset = mp->header_size / ROC_ALIGN;
+
+	/* Use driver specific mp->pool_config to override aura config */
+	if (mp->pool_config != NULL)
+		memcpy(&aura, mp->pool_config, sizeof(struct npa_aura_s));
+
+	rc = roc_npa_pool_create(&aura_handle, block_size, block_count, &aura,
+				 &pool);
+	if (rc) {
+		plt_err("Failed to alloc pool or aura rc=%d", rc);
+		goto error;
+	}
+
+	/* Store aura_handle for future queue operations */
+	mp->pool_id = aura_handle;
+	plt_npa_dbg("block_sz=%lu block_count=%d aura_handle=0x%" PRIx64,
+		    block_size, block_count, aura_handle);
+
+	return 0;
+error:
+	return rc;
+}
+
+void
+cnxk_mempool_free(struct rte_mempool *mp)
+{
+	int rc = 0;
+
+	plt_npa_dbg("aura_handle=0x%" PRIx64, mp->pool_id);
+	rc = roc_npa_pool_destroy(mp->pool_id);
+	if (rc)
+		plt_err("Failed to free pool or aura rc=%d", rc);
+}
+
+int
+cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs,
+		      void *vaddr, rte_iova_t iova, size_t len,
+		      rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg)
+{
+	size_t total_elt_sz, off;
+	int num_elts;
+
+	if (iova == RTE_BAD_IOVA)
+		return -EINVAL;
+
+	total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
+
+	/* Align object start address to a multiple of total_elt_sz */
+	off = total_elt_sz - ((((uintptr_t)vaddr - 1) % total_elt_sz) + 1);
+
+	if (len < off)
+		return -EINVAL;
+
+	vaddr = (char *)vaddr + off;
+	iova += off;
+	len -= off;
+	num_elts = len / total_elt_sz;
+
+	plt_npa_dbg("iova %" PRIx64 ", aligned iova %" PRIx64 "", iova - off,
+		    iova);
+	plt_npa_dbg("length %" PRIu64 ", aligned length %" PRIu64 "",
+		    (uint64_t)(len + off), (uint64_t)len);
+	plt_npa_dbg("element size %" PRIu64 "", (uint64_t)total_elt_sz);
+	plt_npa_dbg("requested objects %" PRIu64 ", possible objects %" PRIu64
+		    "", (uint64_t)max_objs, (uint64_t)num_elts);
+
+	roc_npa_aura_op_range_set(mp->pool_id, iova,
+				  iova + num_elts * total_elt_sz);
+
+	if (roc_npa_pool_range_update_check(mp->pool_id) < 0)
+		return -EBUSY;
+
+	return rte_mempool_op_populate_helper(
+		mp, RTE_MEMPOOL_POPULATE_F_ALIGN_OBJ, max_objs, vaddr, iova,
+		len, obj_cb, obj_cb_arg);
+}
diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build
index 0be0802373..52244e728b 100644
--- a/drivers/mempool/cnxk/meson.build
+++ b/drivers/mempool/cnxk/meson.build
@@ -8,6 +8,7 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')
 	subdir_done()
 endif
 
-sources = files('cnxk_mempool.c')
+sources = files('cnxk_mempool.c',
+		'cnxk_mempool_ops.c')
 
 deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_cnxk', 'mempool']
-- 
2.31.0


  parent reply	other threads:[~2021-04-08  9:51 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-05 16:21 [dpdk-dev] [PATCH 0/6] Add Marvell CNXK mempool driver Ashwin Sekhar T K
2021-03-05 16:21 ` [dpdk-dev] [PATCH 1/6] mempool/cnxk: add build infra and device probe Ashwin Sekhar T K
2021-03-28  9:11   ` Jerin Jacob
2021-03-05 16:21 ` [dpdk-dev] [PATCH 2/6] mempool/cnxk: add generic ops Ashwin Sekhar T K
2021-03-28  9:15   ` Jerin Jacob
2021-03-05 16:21 ` [dpdk-dev] [PATCH 3/6] mempool/cnxk: add cn9k mempool ops Ashwin Sekhar T K
2021-03-05 16:21 ` [dpdk-dev] [PATCH 4/6] mempool/cnxk: add base cn10k " Ashwin Sekhar T K
2021-03-28  9:19   ` Jerin Jacob
2021-03-05 16:21 ` [dpdk-dev] [PATCH 5/6] mempool/cnxk: add cn10k batch enqueue/dequeue support Ashwin Sekhar T K
2021-03-28  9:22   ` Jerin Jacob
2021-03-05 16:21 ` [dpdk-dev] [PATCH 6/6] doc: add Marvell CNXK mempool documentation Ashwin Sekhar T K
2021-03-28  9:06   ` Jerin Jacob
2021-04-03 13:44 ` [dpdk-dev] [PATCH v2 00/11] Add Marvell CNXK mempool driver Ashwin Sekhar T K
2021-04-03 14:17 ` [dpdk-dev] [PATCH v2 01/11] mempool/cnxk: add build infra and doc Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 02/11] mempool/cnxk: add device probe/remove Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 03/11] mempool/cnxk: add generic ops Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 04/11] mempool/cnxk: register lf init/fini callbacks Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 05/11] mempool/cnxk: add cn9k mempool ops Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 06/11] mempool/cnxk: add cn9k optimized mempool enqueue/dequeue Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 07/11] mempool/cnxk: add cn10k mempool ops Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 08/11] mempool/cnxk: add batch op init Ashwin Sekhar T K
2021-04-03 14:34     ` Jerin Jacob
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 09/11] mempool/cnxk: add cn10k batch enqueue op Ashwin Sekhar T K
2021-04-03 14:31     ` Jerin Jacob
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 10/11] mempool/cnxk: add cn10k get count op Ashwin Sekhar T K
2021-04-03 14:17   ` [dpdk-dev] [PATCH v2 11/11] mempool/cnxk: add cn10k batch dequeue op Ashwin Sekhar T K
2021-04-06 15:11 ` [dpdk-dev] [PATCH v3 00/11] Add Marvell CNXK mempool driver Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 01/11] mempool/cnxk: add build infra and doc Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 02/11] mempool/cnxk: add device probe/remove Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 03/11] mempool/cnxk: add generic ops Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 04/11] mempool/cnxk: register plt init callback Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 05/11] mempool/cnxk: add cn9k mempool ops Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 06/11] mempool/cnxk: add cn9k optimized mempool enqueue/dequeue Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 07/11] mempool/cnxk: add cn10k mempool ops Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 08/11] mempool/cnxk: add batch op init Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 09/11] mempool/cnxk: add cn10k batch enqueue op Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 10/11] mempool/cnxk: add cn10k get count op Ashwin Sekhar T K
2021-04-06 15:11   ` [dpdk-dev] [PATCH v3 11/11] mempool/cnxk: add cn10k batch dequeue op Ashwin Sekhar T K
2021-04-08  8:59   ` [dpdk-dev] [PATCH v3 00/11] Add Marvell CNXK mempool driver Jerin Jacob
2021-04-08  9:50 ` [dpdk-dev] [PATCH v4 " Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 01/11] mempool/cnxk: add build infra and doc Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 02/11] mempool/cnxk: add device probe/remove Ashwin Sekhar T K
2021-04-08  9:50   ` Ashwin Sekhar T K [this message]
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 04/11] mempool/cnxk: register plt init callback Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 05/11] mempool/cnxk: add cn9k mempool ops Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 06/11] mempool/cnxk: add cn9k optimized mempool enqueue/dequeue Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 07/11] mempool/cnxk: add cn10k mempool ops Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 08/11] mempool/cnxk: add batch op init Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 09/11] mempool/cnxk: add cn10k batch enqueue op Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 10/11] mempool/cnxk: add cn10k get count op Ashwin Sekhar T K
2021-04-08  9:50   ` [dpdk-dev] [PATCH v4 11/11] mempool/cnxk: add cn10k batch dequeue op Ashwin Sekhar T K
2021-04-09  6:39   ` [dpdk-dev] [PATCH v4 00/11] Add Marvell CNXK mempool driver Jerin Jacob

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