From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79D18A0C46; Thu, 8 Apr 2021 22:50:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5D2414121A; Thu, 8 Apr 2021 22:49:48 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id DB8B3141210 for ; Thu, 8 Apr 2021 22:49:45 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 8 Apr 2021 23:49:41 +0300 Received: from nvidia.com (c-236-0-60-063.mtl.labs.mlnx [10.236.0.63]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 138KnAJT028067; Thu, 8 Apr 2021 23:49:41 +0300 From: Shiri Kuzin To: dev@dpdk.org Cc: matan@nvidia.com, gakhil@marvell.com, suanmingm@nvidia.com, Dekel Peled Date: Thu, 8 Apr 2021 23:48:35 +0300 Message-Id: <20210408204849.9543-11-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210408204849.9543-1-shirik@nvidia.com> References: <1615447568-260965-1-git-send-email-matan@nvidia.com> <20210408204849.9543-1-shirik@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 10/24] common/mlx5: add crypto BSF struct and defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled This patch adds the struct defining crypto BSF segment of UMR WQE, and the related value definitions and offsets. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ca2e70881d..736badb6df 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1096,6 +1096,72 @@ struct mlx5_ifc_create_mkey_in_bits { u8 klm_pas_mtt[][0x20]; }; +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, -- 2.21.0