From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6287AA0C46; Thu, 8 Apr 2021 22:51:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C594D141250; Thu, 8 Apr 2021 22:49:57 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 16415141229 for ; Thu, 8 Apr 2021 22:49:51 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 8 Apr 2021 23:49:46 +0300 Received: from nvidia.com (c-236-0-60-063.mtl.labs.mlnx [10.236.0.63]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 138KnAJX028067; Thu, 8 Apr 2021 23:49:46 +0300 From: Shiri Kuzin To: dev@dpdk.org Cc: matan@nvidia.com, gakhil@marvell.com, suanmingm@nvidia.com, Dekel Peled Date: Thu, 8 Apr 2021 23:48:39 +0300 Message-Id: <20210408204849.9543-15-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210408204849.9543-1-shirik@nvidia.com> References: <1615447568-260965-1-git-send-email-matan@nvidia.com> <20210408204849.9543-1-shirik@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 14/24] common/mlx5: add crypto register structs and defs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Encryption key management requires use of several related registers. This patch adds the relevant structs and values, according to PRM definitions. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 69d6de8cbd..4518304889 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3232,6 +3232,10 @@ enum { enum { MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, }; struct mlx5_ifc_register_mtutc_bits { @@ -3249,6 +3253,43 @@ struct mlx5_ifc_register_mtutc_bits { #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + struct mlx5_ifc_parse_graph_arc_bits { u8 start_inner_tunnel[0x1]; u8 reserved_at_1[0x7]; -- 2.21.0