From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27149A0524; Tue, 13 Apr 2021 06:07:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC578160A63; Tue, 13 Apr 2021 06:07:03 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id C3546160A56 for ; Tue, 13 Apr 2021 06:06:59 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from lizh@nvidia.com) with SMTP; 13 Apr 2021 07:06:57 +0300 Received: from nvidia.com (c-135-185-1-009.mtl.labs.mlnx [10.135.185.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13D46u8I018937; Tue, 13 Apr 2021 07:06:56 +0300 From: Li Zhang To: dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, shahafs@nvidia.com Cc: dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com Date: Tue, 13 Apr 2021 07:06:52 +0300 Message-Id: <20210413040653.29210-2-lizh@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210413040653.29210-1-lizh@nvidia.com> References: <20210331092319.1446618-1-lizh@nvidia.com> <20210413040653.29210-1-lizh@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 1/2] common/mlx5: add meter mode definition in PRM file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add meter mode definitions in PRM file Signed-off-by: Li Zhang Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c6d8060bb9..efa5ae67bf 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2297,6 +2297,13 @@ struct mlx5_ifc_flow_meter_parameters_bits { #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 +enum { + MLX5_METER_MODE_IP_LEN = 0x0, + MLX5_METER_MODE_L2_LEN = 0x1, + MLX5_METER_MODE_L2_IPG_LEN = 0x2, + MLX5_METER_MODE_PKT = 0x3, +}; + enum { MLX5_CQE_SIZE_64B = 0x0, MLX5_CQE_SIZE_128B = 0x1, @@ -2671,6 +2678,7 @@ struct mlx5_aso_mtr_dseg { #define ASO_DSEG_VALID_OFFSET 31 #define ASO_DSEG_BO_OFFSET 30 #define ASO_DSEG_SC_OFFSET 28 +#define ASO_DSEG_MTR_MODE 24 #define ASO_DSEG_CBS_EXP_OFFSET 24 #define ASO_DSEG_CBS_MAN_OFFSET 16 #define ASO_DSEG_CIR_EXP_MASK 0x1F -- 2.27.0