From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E180DA0524; Tue, 13 Apr 2021 16:28:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 72394161080; Tue, 13 Apr 2021 16:27:15 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 5712A16107B for ; Tue, 13 Apr 2021 16:27:13 +0200 (CEST) IronPort-SDR: sJGiyE7BjKQtoeaa1U6HMwcvI9+5vrZtSMpJHQ9gUbMnJpbpZe60rCL2pY8c3TM+jTraYlGCWT u9hY0lqt07lA== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="214904273" X-IronPort-AV: E=Sophos;i="5.82,219,1613462400"; d="scan'208";a="214904273" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 07:27:12 -0700 IronPort-SDR: xNnOTHY96X55hIGYlmxwjADqUne+ZZgqksakqVjT2zb9F1WPRIB/9+Zv8DKsEt1aGw3qUlHdP8 mqMzhGm13nhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,219,1613462400"; d="scan'208";a="417875243" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 13 Apr 2021 07:27:11 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , Karol Kolacinski Date: Tue, 13 Apr 2021 22:30:34 +0800 Message-Id: <20210413143038.2621294-11-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210413143038.2621294-1-qi.z.zhang@intel.com> References: <20210329141411.2395069-1-qi.z.zhang@intel.com> <20210413143038.2621294-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 10/14] net/ice/base: add set/get GPIO helper functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add helper functions to set the GPIO pin state or get the value of a GPIO signal that's the part of the topology based on AQ commands. This change is needed to setup GPIO pins state for PTP, SyncE etc. Signed-off-by: Karol Kolacinski Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 11 +++++ drivers/net/ice/base/ice_common.c | 58 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 6 +++ 3 files changed, 75 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index f9a741e99f..6b662b3889 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1701,6 +1701,16 @@ struct ice_aqc_set_port_id_led { u8 rsvd[13]; }; +/* Set/Get GPIO (direct, 0x06EC/0x06ED) */ +struct ice_aqc_gpio { + __le16 gpio_ctrl_handle; +#define ICE_AQC_GPIO_HANDLE_S 0 +#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) + u8 gpio_num; + u8 gpio_val; + u8 rsvd[12]; +}; + /* Read/Write SFF EEPROM command (indirect 0x06EE) */ struct ice_aqc_sff_eeprom { u8 lport_num; @@ -2865,6 +2875,7 @@ struct ice_aq_desc { struct ice_aqc_restart_an restart_an; struct ice_aqc_i2c read_write_i2c; struct ice_aqc_read_i2c_resp read_i2c_resp; + struct ice_aqc_gpio read_write_gpio; struct ice_aqc_sff_eeprom read_write_sff_param; struct ice_aqc_set_port_id_led set_port_id_led; struct ice_aqc_get_sw_cfg get_sw_conf; diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index befaa83a4b..2424f3b4b3 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -4860,6 +4860,64 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); } +/** + * ice_aq_set_gpio + * @hw: pointer to the hw struct + * @gpio_ctrl_handle: GPIO controller node handle + * @pin_idx: IO Number of the GPIO that needs to be set + * @value: SW provide IO value to set in the LSB + * @cd: pointer to command details structure or NULL + * + * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology + */ +enum ice_status +ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, + struct ice_sq_cd *cd) +{ + struct ice_aqc_gpio *cmd; + struct ice_aq_desc desc; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); + cmd = &desc.params.read_write_gpio; + cmd->gpio_ctrl_handle = gpio_ctrl_handle; + cmd->gpio_num = pin_idx; + cmd->gpio_val = value ? 1 : 0; + + return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); +} + +/** + * ice_aq_get_gpio + * @hw: pointer to the hw struct + * @gpio_ctrl_handle: GPIO controller node handle + * @pin_idx: IO Number of the GPIO that needs to be set + * @value: IO value read + * @cd: pointer to command details structure or NULL + * + * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of + * the topology + */ +enum ice_status +ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, + bool *value, struct ice_sq_cd *cd) +{ + struct ice_aqc_gpio *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); + cmd = &desc.params.read_write_gpio; + cmd->gpio_ctrl_handle = gpio_ctrl_handle; + cmd->gpio_num = pin_idx; + + status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); + if (status) + return status; + + *value = !!cmd->gpio_val; + return ICE_SUCCESS; +} + /** * ice_fw_supports_link_override * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index f9e3ed1d67..62b5052797 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -220,6 +220,12 @@ enum ice_status ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, struct ice_aqc_txsched_elem_data *buf); enum ice_status +ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, + struct ice_sq_cd *cd); +enum ice_status +ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, + bool *value, struct ice_sq_cd *cd); +enum ice_status ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, struct ice_sq_cd *cd); bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); -- 2.26.2