From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B5EDA0547; Sun, 18 Apr 2021 17:52:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D5B2410E5; Sun, 18 Apr 2021 17:52:01 +0200 (CEST) Received: from NAM04-SN1-obe.outbound.protection.outlook.com (mail-eopbgr700044.outbound.protection.outlook.com [40.107.70.44]) by mails.dpdk.org (Postfix) with ESMTP id 4FED1410D7 for ; Sun, 18 Apr 2021 17:51:59 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Un+KOKp9PUMrNyMZgTxOQ1b5OYWl37efQBzd+xwzQI3ZEkE8TYjCs+sH6dhWOTUc2gOlC9IYtij/4YcPeZ8f587QN6vjaisuzOOHW5NZ2+XUL3vHvdKiyUOSwC6J5PhMuCiv06KXzMsNM6UrE6BRbZudo696UecKDtTyZk48LOSGurs17S6TcZT4G3pjZpzKTgybT+I7BevlaGBCbc6t6eMQQxiLZr/HU96turg2VXzP0ZN+5p1tpsT5+xqBoysnstXyOlHqVvC1PdZFHJr2XopvRwWKV/UHqVpqgB5qoPKUPd3Zirb6bIguLWL80R4X9sglp7zW3LGdIH2ABUntKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JGdtJ4vsFGGXFzEwH6uyWQqIVNRzDIeguQ+EbvdwM88=; b=gXgG6BtT1SNRYE56eem0SQNc0yQBy+QNU8S2o22JuhZrpulBuMwYsCQYh1ElCfEHSNnnNnqxVRGBypk5RIA1677XAIR5heH+cwUCDTbEfmTMjhtu69156rCHRXhmb+8i1lN+ttVnLPCozgDzG+aMqB0unqtA4sZanko7Xg1gTCbAsZm35UmOoBHkOQsG0mNvfJwi84EV+4FS/Q6KjhR42lfiXhjPfMLGLUGDyqqwiuhP8U7jUfwbqVhg2su6+OzFr2UPP3qZGgfdIaDHrQYCD84svXQBb4DdIWaI3nPN53hE1dkp7iQM4lJ7V7CGQgOIhWiqxGsT+5fW74nTyflfNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JGdtJ4vsFGGXFzEwH6uyWQqIVNRzDIeguQ+EbvdwM88=; b=g4Ny8UPTRZvPbpO29jEMjTCyLXpgfq/jH6YyIyKSu5zmNRDL0HrbCDewdXnbdOObmzoxGst3M6vQCV4U7OTCnwhfqEuVhkHjAKn3smm1QaJ6sxTjqdQ1ni2OyhjZhmD4hQwOXhuxToIsYX5t/cbxqmlY2ZNriw8bG9NyAJuQH10e/zxx0ODDlm7+3oIqynYHrCjhhVcWlMNu9dFaBz8uuG0BpDKmuOO+vb3c+AUtdRFMeAbXxtGYq7O0Lx+t9B2LPJlLaYvEk3In8YjrRs8TEpKG2j2D/33IV744S0j/3KkWwAT6RC1P+Xu3JtBb0LJHfvlPVjzJAri68jTk4SPkOQ== Received: from MW4PR04CA0050.namprd04.prod.outlook.com (2603:10b6:303:6a::25) by DM5PR12MB2565.namprd12.prod.outlook.com (2603:10b6:4:b8::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4042.16; Sun, 18 Apr 2021 15:51:57 +0000 Received: from CO1NAM11FT004.eop-nam11.prod.protection.outlook.com (2603:10b6:303:6a:cafe::e5) by MW4PR04CA0050.outlook.office365.com (2603:10b6:303:6a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4042.16 via Frontend Transport; Sun, 18 Apr 2021 15:51:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT004.mail.protection.outlook.com (10.13.175.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4042.16 via Frontend Transport; Sun, 18 Apr 2021 15:51:56 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 18 Apr 2021 15:51:53 +0000 From: Gregory Etelson To: CC: , , , , , , , , , , , Date: Sun, 18 Apr 2021 18:51:35 +0300 Message-ID: <20210418155136.23684-2-getelson@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418155136.23684-1-getelson@nvidia.com> References: <20210418155136.23684-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 01d823e5-6c34-4378-d282-08d90281e53f X-MS-TrafficTypeDiagnostic: DM5PR12MB2565: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9wc02oNIlAaIiQNotZx/++VruA9x6kBcSYEucF1/18swDn2RTOpVAukUAXLeE3pzt6DHshns/xxeqG8ZLL4ZoDohVzkBIGtyFDV4BHayOLUYBGV6zs4vvPFlHUgTSsDIBLRQ/+R+jl46tuCxlR2XzHMhrswsTd9saQPb/2msZ2FFOKzOtE8a3aLdGpdrY9Mc1x53ksymEU+0VkTcWDam1U5VD5Tv4AVhQQAVu9hjY+1bc4NRzTmcLtkUeJ35l0sV+830IfYQJAi7IlAvV3uz7rANM5ZM3sLMw/FVmnGrsqkFJolk2sl3MCt+/iXusQ0x+9+ezvvBZt6Cu78XTkAjU4VSY8icHJe4MqvFfuYoTOlL4dQcjXCRZ/Qlg3DpYq7kW0AlGsV1UVdPu7GF7xc89zChFVUvAw/h2jfNAeBgtH3qfP4VX9G/DLZEAMsOi2rt8df+t1K6ZOZLPOQgoT+Hr8duOodeeK7r8xjL9+KutD/Sh1/I9UPUL4LEVYe3y08UiUT2owU9ha+vtQTmrj07W/+xFsMP2eAjkBXf7u4Ef0Cr8i07s6UAN6qJ9RbsisS6Dqxod60XnGWvh/SGwKgtmrtGXlQDvBzV8uaVM/Vp0xUTj78f2ISDequf/h55gJON/xxP5kA8XtC/JdISd5XHjHksaNfyyEj8kYJFioTnDtU= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(396003)(346002)(39860400002)(376002)(36840700001)(46966006)(6862004)(478600001)(70586007)(107886003)(70206006)(82310400003)(5660300002)(2906002)(82740400003)(6286002)(16526019)(54906003)(83380400001)(1076003)(36756003)(426003)(316002)(356005)(186003)(26005)(7636003)(8676002)(336012)(4326008)(47076005)(86362001)(6666004)(2616005)(55016002)(7696005)(8936002)(6636002)(36906005)(36860700001)(37006003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2021 15:51:56.8848 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01d823e5-6c34-4378-d282-08d90281e53f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2565 Subject: [dpdk-dev] [PATCH v6 1/2] ethdev: add packet integrity checks X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ori Kam Currently, DPDK application can offload the checksum check, and report it in the mbuf. However, as more and more applications are offloading some or all logic and action to the HW, there is a need to check the packet integrity so the right decision can be taken. The application logic can be positive meaning if the packet is valid jump / do actions, or negative if packet is not valid jump to SW / do actions (like drop) and add default flow (match all in low priority) that will direct the miss packet to the miss path. Since currently rte_flow works in positive way the assumption is that the positive way will be the common way in this case also. When thinking what is the best API to implement such feature, we need to consider the following (in no specific order): 1. API breakage. 2. Simplicity. 3. Performance. 4. HW capabilities. 5. rte_flow limitation. 6. Flexibility. First option: Add integrity flags to each of the items. For example add checksum_ok to ipv4 item. Pros: 1. No new rte_flow item. 2. Simple in the way that on each item the app can see what checks are available. Cons: 1. API breakage. 2. increase number of flows, since app can't add global rule and must have dedicated flow for each of the flow combinations, for example matching on icmp traffic or UDP/TCP traffic with IPv4 / IPv6 will result in 5 flows. Second option: dedicated item Pros: 1. No API breakage, and there will be no for some time due to having extra space. (by using bits) 2. Just one flow to support the icmp or UDP/TCP traffic with IPv4 / IPv6. 3. Simplicity application can just look at one place to see all possible checks. 4. Allow future support for more tests. Cons: 1. New item, that holds number of fields from different items. For starter the following bits are suggested: 1. packet_ok - means that all HW checks depending on packet layer have passed. This may mean that in some HW such flow should be splited to number of flows or fail. 2. l2_ok - all check for layer 2 have passed. 3. l3_ok - all check for layer 3 have passed. If packet doesn't have l3 layer this check should fail. 4. l4_ok - all check for layer 4 have passed. If packet doesn't have l4 layer this check should fail. 5. l2_crc_ok - the layer 2 crc is O.K. 6. ipv4_csum_ok - IPv4 checksum is O.K. it is possible that the IPv4 checksum will be O.K. but the l3_ok will be 0. it is not possible that checksum will be 0 and the l3_ok will be 1. 7. l4_csum_ok - layer 4 checksum is O.K. 8. l3_len_OK - check that the reported layer 3 len is smaller than the frame len. Example of usage: 1. check packets from all possible layers for integrity. flow create integrity spec packet_ok = 1 mask packet_ok = 1 ..... 2. Check only packet with layer 4 (UDP / TCP) flow create integrity spec l3_ok = 1, l4_ok = 1 mask l3_ok = 1 l4_ok = 1 Signed-off-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 20 +++++++++++ doc/guides/rel_notes/release_21_05.rst | 5 +++ lib/librte_ethdev/rte_flow.h | 49 ++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index e1b93ecedf..1dd2301a07 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1398,6 +1398,26 @@ Matches a eCPRI header. - ``hdr``: eCPRI header definition (``rte_ecpri.h``). - Default ``mask`` matches nothing, for all eCPRI messages. +Item: ``PACKET_INTEGRITY_CHECKS`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Matches packet integrity. +For some devices application needs to enable integration checks in HW +before using this item. + +- ``level``: the encapsulation level that should be checked. level 0 means the + default PMD mode (Can be inner most / outermost). value of 1 means outermost + and higher value means inner header. See also RSS level. +- ``packet_ok``: All HW packet integrity checks have passed based on the max + layer of the packet. +- ``l2_ok``: all layer 2 HW integrity checks passed. +- ``l3_ok``: all layer 3 HW integrity checks passed. +- ``l4_ok``: all layer 4 HW integrity checks passed. +- ``l2_crc_ok``: layer 2 crc check passed. +- ``ipv4_csum_ok``: ipv4 checksum check passed. +- ``l4_csum_ok``: layer 4 checksum check passed. +- ``l3_len_ok``: the layer 3 len is smaller than the frame len. + Actions ~~~~~~~ diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 82ee71152f..b1c90f4d9f 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -55,6 +55,11 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Added packet integrity match to flow rules.** + + * Added ``RTE_FLOW_ITEM_TYPE_INTEGRITY`` flow item. + * Added ``rte_flow_item_integrity`` data structure. + * **Added support for Marvell CN10K SoC drivers.** Added Marvell CN10K SoC support. Marvell CN10K SoC are based on Octeon 10 diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h index 203c4cde9a..bef5c770c5 100644 --- a/lib/librte_ethdev/rte_flow.h +++ b/lib/librte_ethdev/rte_flow.h @@ -551,6 +551,17 @@ enum rte_flow_item_type { * See struct rte_flow_item_geneve_opt */ RTE_FLOW_ITEM_TYPE_GENEVE_OPT, + + /** + * [META] + * + * Matches on packet integrity. + * For some devices application needs to enable integration checks in HW + * before using this item. + * + * See struct rte_flow_item_integrity. + */ + RTE_FLOW_ITEM_TYPE_INTEGRITY, }; /** @@ -1685,6 +1696,44 @@ rte_flow_item_geneve_opt_mask = { }; #endif +__extension__ +struct rte_flow_item_integrity { + /**< Tunnel encapsulation level the item should apply to. + * @see rte_flow_action_rss + */ + uint32_t level; + union { + struct { + /**< The packet is valid after passing all HW checks. */ + uint64_t packet_ok:1; + /**< L2 layer is valid after passing all HW checks. */ + uint64_t l2_ok:1; + /**< L3 layer is valid after passing all HW checks. */ + uint64_t l3_ok:1; + /**< L4 layer is valid after passing all HW checks. */ + uint64_t l4_ok:1; + /**< L2 layer CRC is valid. */ + uint64_t l2_crc_ok:1; + /**< IPv4 layer checksum is valid. */ + uint64_t ipv4_csum_ok:1; + /**< L4 layer checksum is valid. */ + uint64_t l4_csum_ok:1; + /**< The l3 length is smaller than the frame length. */ + uint64_t l3_len_ok:1; + uint64_t reserved:56; + }; + uint64_t value; + }; +}; + +#ifndef __cplusplus +static const struct rte_flow_item_integrity +rte_flow_item_integrity_mask = { + .level = 0, + .value = 0, +}; +#endif + /** * Matching pattern item definition. * -- 2.25.1