From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 474B7A0548; Wed, 21 Apr 2021 07:22:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D7D24193C; Wed, 21 Apr 2021 07:22:41 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 4CAE64181F for ; Wed, 21 Apr 2021 07:22:38 +0200 (CEST) IronPort-SDR: vegydemnzU6dOWK0B3JgODGvhx03VGVV+Wt1ve5PkfhMkv61IY+DnTOhUJLolu8qgwZlT4pAgL bYCTTL1tX1YQ== X-IronPort-AV: E=McAfee;i="6200,9189,9960"; a="195197397" X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="195197397" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2021 22:22:37 -0700 IronPort-SDR: B9JUqvFd/K8qNHZYNeVC2Dcbn+ushvSWJnc8iJ7mRUQhdV6kPAQTxIfITGBpxP+zDkxonvs6GG 6j8tf87//9kA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="427380647" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga008.jf.intel.com with ESMTP; 20 Apr 2021 22:22:35 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Ray Kinsella , Neil Horman , Gaetan Rivet Date: Wed, 21 Apr 2021 13:02:41 +0800 Message-Id: <20210421050243.130585-2-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210421050243.130585-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v1 1/3] bus/pci: enable PCI master in command register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This adds the support to set 'Bus Master Enable' bit in the PCI command register. Signed-off-by: Haiyue Wang --- drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++ drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++ drivers/bus/pci/version.map | 1 + lib/librte_pci/rte_pci.h | 4 ++++ 4 files changed, 37 insertions(+) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index ee7f966358..b631cb9c7e 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap) return 0; } +int +rte_pci_enable_bus_master(struct rte_pci_device *dev) +{ + uint16_t cmd; + + if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) { + RTE_LOG(ERR, EAL, "error in reading PCI command register\n"); + return -1; + } + + cmd |= RTE_PCI_COMMAND_MASTER; + + if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) { + RTE_LOG(ERR, EAL, "error in writing PCI command register\n"); + return -1; + } + + return 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 64886b4731..83caf477ba 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f); __rte_experimental off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); +/** + * Enables Bus Master for device's PCI command register. + * + * @param dev + * A pointer to rte_pci_device structure. + * + * @return + * 0 on success, -1 on error in PCI config space read/write. + */ +__rte_experimental +int rte_pci_enable_bus_master(struct rte_pci_device *dev); + /** * Register a PCI driver. * diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map index f33ed0abd1..b271e48a8f 100644 --- a/drivers/bus/pci/version.map +++ b/drivers/bus/pci/version.map @@ -20,5 +20,6 @@ DPDK_21 { EXPERIMENTAL { global: + rte_pci_enable_bus_master; rte_pci_find_ext_capability; }; diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h index a8f8e404a9..1f33d687f4 100644 --- a/lib/librte_pci/rte_pci.h +++ b/lib/librte_pci/rte_pci.h @@ -32,6 +32,10 @@ extern "C" { #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ +#define RTE_PCI_COMMAND 0x04 /* 16 bits */ + +/* PCI Command Register */ +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ /* PCI Express capability registers */ #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */ -- 2.31.1