From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1FFC7A0547; Wed, 21 Apr 2021 18:35:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E1CE7410F9; Wed, 21 Apr 2021 18:35:13 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 0504041B82 for ; Wed, 21 Apr 2021 18:35:12 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMd005314; Wed, 21 Apr 2021 19:35:11 +0300 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, asafp@nvidia.com, odia@nvidia.com, stable@dpdk.org Date: Wed, 21 Apr 2021 19:34:39 +0300 Message-Id: <20210421163441.17240-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210421163441.17240-1-talshn@nvidia.com> References: <20210421163441.17240-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" mlx5 offloads which are unsupported on Windows are currently disabled by checks with IBV/DV flags which are irrelevant to Windows. The checks are removed until they are fully available. Fixes: 93f4ece91a1f ("net/mlx5: spawn ethdev ports on Windows") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 814063b5ce..5e53042b85 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -359,11 +359,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->swp = 0; config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; - if (RTE_CACHE_LINE_SIZE == 128 && - !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) - cqe_comp = 0; - else - cqe_comp = 1; + cqe_comp = 0; config->cqe_comp = cqe_comp; DRV_LOG(DEBUG, "tunnel offloading is not supported"); config->tunnel_en = 0; @@ -424,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = mlx5_dev_check_sibling_config(priv, config); if (err) goto error; - config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & - IBV_DEVICE_RAW_IP_CSUM); DRV_LOG(DEBUG, "checksum offloading is %ssupported", (config->hw_csum ? "" : "not ")); DRV_LOG(DEBUG, "counters are not supported"); @@ -439,19 +433,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", config->ind_table_max_size); - config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & - IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); DRV_LOG(DEBUG, "VLAN stripping is %ssupported", (config->hw_vlan_strip ? "" : "not ")); - config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & - IBV_RAW_PACKET_CAP_SCATTER_FCS); if (config->hw_padding) { DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); config->hw_padding = 0; } - config->tso = (sh->device_attr.max_tso > 0 && - (sh->device_attr.tso_supported_qpts & - (1 << IBV_QPT_RAW_PACKET))); if (config->tso) config->tso_max_payload_sz = sh->device_attr.max_tso; DRV_LOG(DEBUG, "%sMPS is %s.", -- 2.16.1.windows.4