From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4BD8A0548; Mon, 26 Apr 2021 19:47:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 101F34122E; Mon, 26 Apr 2021 19:46:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 339C441212 for ; Mon, 26 Apr 2021 19:46:07 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13QHivac030137; Mon, 26 Apr 2021 10:46:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mhDIlHQXJ/N0awFOlXBGln+QgEubzqgzsO5pWyizRyo=; b=Qo/dHDrBiiKMMAQ254qYyZdh23fU5meHA3B4F4pZiRPNkBhR6YCacAYt/XvMyjYVppoN YWh24Fw8ak55+8GPHOwAeWTcBr3yf30cMX/Dz1uMFr5BbmqBENJxJQjH/YJFYejI4zWd ifXp2Frf0ISQT6FXl7rOG1jc7KZGXiIJdsh99VcW0+lEIlsl+o98qjhkvZFEEBw8PVQn /PwM2aiISL+0GDhCwVP/NM92GyZUmCR2zPcp/unvoUSLoiL2VrpGaDNyD+l7MHd/f8ll OOa+sUznyoN0pBQ6l1rp9im1DR1qQqbbojIx6+gXHxotMdc+5I1nn4g3zfBuJD6ilFHn UA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 385tvvhdj5-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 26 Apr 2021 10:46:06 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Apr 2021 10:46:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Apr 2021 10:46:04 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 2F7575B6C9B; Mon, 26 Apr 2021 10:46:01 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Anatoly Burakov CC: Date: Mon, 26 Apr 2021 23:14:27 +0530 Message-ID: <20210426174441.2302-21-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210426174441.2302-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> <20210426174441.2302-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: dryaGh3IiYnU49oEfmH9EZ5lE6WEEFTA X-Proofpoint-ORIG-GUID: dryaGh3IiYnU49oEfmH9EZ5lE6WEEFTA X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-26_09:2021-04-26, 2021-04-26 signatures=0 Subject: [dpdk-dev] [PATCH v2 20/33] event/cnxk: support event timer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter aka TIM initialization on SSO probe. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 6 ++++ drivers/event/cnxk/cnxk_eventdev.c | 3 ++ drivers/event/cnxk/cnxk_eventdev.h | 2 ++ drivers/event/cnxk/cnxk_tim_evdev.c | 47 +++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_evdev.h | 44 +++++++++++++++++++++++++++ drivers/event/cnxk/meson.build | 1 + 6 files changed, 103 insertions(+) create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.c create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.h diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index b2684d431..662df2971 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -35,6 +35,10 @@ Features of the OCTEON CNXK SSO PMD are: - Open system with configurable amount of outstanding events limited only by DRAM - HW accelerated dequeue timeout support to enable power management +- HW managed event timers support through TIM, with high precision and + time granularity of 2.5us on CN9K and 1us on CN10K. +- Up to 256 TIM rings aka event timer adapters. +- Up to 8 rings traversed in parallel. Prerequisites and Compilation procedure --------------------------------------- @@ -101,3 +105,5 @@ Debugging Options +===+============+=======================================================+ | 1 | SSO | --log-level='pmd\.event\.cnxk,8' | +---+------------+-------------------------------------------------------+ + | 2 | TIM | --log-level='pmd\.event\.cnxk\.timer,8' | + +---+------------+-------------------------------------------------------+ diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index dbd35ca5d..c404bb586 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -582,6 +582,8 @@ cnxk_sso_init(struct rte_eventdev *event_dev) dev->nb_event_queues = 0; dev->nb_event_ports = 0; + cnxk_tim_init(&dev->sso); + return 0; error: @@ -598,6 +600,7 @@ cnxk_sso_fini(struct rte_eventdev *event_dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + cnxk_tim_fini(); roc_sso_rsrc_fini(&dev->sso); roc_sso_dev_fini(&dev->sso); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index d52408e5a..81bb3488a 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -14,6 +14,8 @@ #include "roc_api.h" +#include "cnxk_tim_evdev.h" + #define CNXK_SSO_XAE_CNT "xae_cnt" #define CNXK_SSO_GGRP_QOS "qos" #define CN9K_SSO_SINGLE_WS "single_ws" diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c new file mode 100644 index 000000000..76b17910f --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#include "cnxk_eventdev.h" +#include "cnxk_tim_evdev.h" + +void +cnxk_tim_init(struct roc_sso *sso) +{ + const struct rte_memzone *mz; + struct cnxk_tim_evdev *dev; + int rc; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return; + + mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME), + sizeof(struct cnxk_tim_evdev), 0, 0); + if (mz == NULL) { + plt_tim_dbg("Unable to allocate memory for TIM Event device"); + return; + } + dev = mz->addr; + + dev->tim.roc_sso = sso; + rc = roc_tim_init(&dev->tim); + if (rc < 0) { + plt_err("Failed to initialize roc tim resources"); + rte_memzone_free(mz); + return; + } + dev->nb_rings = rc; + dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; +} + +void +cnxk_tim_fini(void) +{ + struct cnxk_tim_evdev *dev = tim_priv_get(); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return; + + roc_tim_fini(&dev->tim); + rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME))); +} diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h new file mode 100644 index 000000000..6cf0adb21 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef __CNXK_TIM_EVDEV_H__ +#define __CNXK_TIM_EVDEV_H__ + +#include +#include +#include +#include + +#include +#include +#include + +#include "roc_api.h" + +#define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev +#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096) + +struct cnxk_tim_evdev { + struct roc_tim tim; + struct rte_eventdev *event_dev; + uint16_t nb_rings; + uint32_t chunk_sz; +}; + +static inline struct cnxk_tim_evdev * +tim_priv_get(void) +{ + const struct rte_memzone *mz; + + mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)); + if (mz == NULL) + return NULL; + + return mz->addr; +} + +void cnxk_tim_init(struct roc_sso *sso); +void cnxk_tim_fini(void); + +#endif /* __CNXK_TIM_EVDEV_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index da386001e..44a300aa0 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -15,6 +15,7 @@ sources = files('cn10k_worker.c', 'cnxk_eventdev.c', 'cnxk_eventdev_selftest.c', 'cnxk_eventdev_stats.c', + 'cnxk_tim_evdev.c', ) deps += ['bus_pci', 'common_cnxk', 'net_cnxk'] -- 2.17.1