From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D98DDA0A02; Tue, 27 Apr 2021 16:05:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 121C441266; Tue, 27 Apr 2021 16:05:28 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 282224125A for ; Tue, 27 Apr 2021 16:05:23 +0200 (CEST) IronPort-SDR: MFW8/DDeUzW1Gff2tTChbOUOWRTaergtlcrNqKnE4ukQSyxidr7lxPRcqYfnGfK6ILIHSh8GQ9 4hu5otSuEjpw== X-IronPort-AV: E=McAfee;i="6200,9189,9967"; a="183994846" X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="183994846" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2021 07:05:23 -0700 IronPort-SDR: bJnxJENfUr5Ln/RvqeSzLQkFIUHOz8VXHuF9Vq7v+ARcftwJIakvbb1itL5I5Pph8ByfqbLTOo mV/gIUB7mZgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="457656376" Received: from npg-dpdk-haiyue-2.sh.intel.com ([10.67.119.63]) by fmsmga002.fm.intel.com with ESMTP; 27 Apr 2021 07:05:21 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, david.marchand@redhat.com, Haiyue Wang , Beilei Xing , Jeff Guo Date: Tue, 27 Apr 2021 21:39:12 +0800 Message-Id: <20210427133912.261993-4-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210427133912.261993-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210427133912.261993-1-haiyue.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4 3/3] net/i40e: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And align the VF reset event handling in device close module as the AVF driver does. Signed-off-by: Haiyue Wang --- drivers/net/i40e/i40e_ethdev_vf.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 3c258ba7c..8b041e94c 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -1212,7 +1212,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev *dev) if (i >= MAX_RESET_WAIT_CNT) return -1; - vf->vf_reset = false; vf->pend_msg &= ~PFMSG_RESET_IMPENDING; return 0; @@ -1391,6 +1390,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg, switch (pf_msg->event) { case VIRTCHNL_EVENT_RESET_IMPENDING: PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event"); + vf->vf_reset = true; rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL); break; @@ -2487,6 +2487,11 @@ i40evf_dev_close(struct rte_eth_dev *dev) i40e_shutdown_adminq(hw); i40evf_disable_irq0(hw); + if (vf->vf_reset) + rte_pci_set_bus_master(RTE_ETH_DEV_TO_PCI(dev), true); + + vf->vf_reset = false; + rte_free(vf->vf_res); vf->vf_res = NULL; rte_free(vf->aq_resp); -- 2.31.1