From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7DE9A0547; Thu, 29 Apr 2021 17:45:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9317F4134B; Thu, 29 Apr 2021 17:45:01 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2040.outbound.protection.outlook.com [40.107.237.40]) by mails.dpdk.org (Postfix) with ESMTP id D83974110F for ; Thu, 29 Apr 2021 17:44:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=S9uy0SraLGNYpn2N3JQDo6RM87+svpHUUbkN4N7m27bgFxlanR5t841Y3IK97TVIy5oqv5HLkMiYZbNUfqL9bdx6lxdlolb0mKwFTxc9VBbMSLZ5I9HYojzHymTEv5G6Y+WdkqG4ggfusSQx01SndAV2HGg2x72zre+DIzhEY9sIFukP7H0Fi6V1xTcsIAe5P9CTnU0iB8hIeLS0okNLZVyQulHKkMCMzVNl2P7CBCZwN4VGsj98izjwX+3Ma6ZRzdii06ZRX/yVcwOezKKgQJyUj3UIGX1vNWFVHQSJo2FKVyswH3cbcYfUmYvSd5i8CxrrC9lVl+RX4KJ9d5ktZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mPr5rMpTdg+eF6DreyYQLjm8SqOm1l6YttcLm5KoD2g=; b=AzwR1trWanlOFs+ZYwiHv616LDuYuJ0kKeQWobmZ8cMXbXiVGulUZ2tHKInNFeecrDJSnPq6kPCrJ4RnrkUAY/v3Bo8eSUkQ72+XezDGfux7tvgypITe8Z8694cnHQypBEMQ3E1U7vEn2uEzJB+a3OocraIlH5lQlhkig2TY6Cz5gcukDbrzLZpUFPYJFd3iM5yay365hkLRqsBS22pK9JrDQHr4hf9b3kAiVSMhy5tNBpVElOSpkrAuRQe9XpppqHa5Q0PlVGApWq5Jb3y3L04qqx3z/C+cY2lHzNrdsVj1XIHsvrtkNpazgsZjKHpGnlGbNsxFeOZ8intcWPtudg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mPr5rMpTdg+eF6DreyYQLjm8SqOm1l6YttcLm5KoD2g=; b=Cc1r8n9WVZhDg0RelpSC6sa01epYRce0NprR+DfYACPAn7knJT2PALh6gApR1mUlVNPZh3Let1iWJtwp+SQzGN64Gqd3FhzGr/fQhbiDuQfYIZ0U+9ctIfQDOtRS5LcAmHX3k0Tb2TJaPu66AqEyhGaBSxD+R6CBIEgdhPxCsEKhhS/qDkjIED6JxXLy7HE8GEGkvLGucksIKrGfmBA69wdSYWarGvvFIJR/u1aTwqptALlkhXw/R8OaekQxtAOkxCIvjr9RkyRGWSoIzGR2tiXnfDCHqdWycSP6JHBTF9+B1xu0cUia4vKVXNFqQ2m0dxd2eDlI9NFWE7RitRBgTw== Received: from DM5PR07CA0103.namprd07.prod.outlook.com (2603:10b6:4:ae::32) by CH0PR12MB5388.namprd12.prod.outlook.com (2603:10b6:610:d7::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.22; Thu, 29 Apr 2021 15:44:54 +0000 Received: from DM6NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:4:ae:cafe::59) by DM5PR07CA0103.outlook.office365.com (2603:10b6:4:ae::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:44:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:44:54 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:52 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:29 +0300 Message-ID: <20210429154335.2820028-11-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 000d64c9-0a8c-49fc-6744-08d90b25bc22 X-MS-TrafficTypeDiagnostic: CH0PR12MB5388: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2043; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PTz7OQph0Kqu0eQc/aau+5UznR1L5IvhMsKZE5ICK8gh30sIiytYYtIL3YNacIdfSL8GDvE8aw49H8sVQTTh+PClR2hA2r+kyJvB8s/5BY5dnZKV2cIz/rZvOMA7bZAQnu3xCVSuEPGPlGMKqY5PdhCVpXJgoWaIT4xcOsgS9uiSgPC3emeOHd2/2dgsSHa1hTvJIrxXWxBUasMzq33CTLGlkq1Z1d9ka0oJ6/XBcv767qOqMpUK0xrqDllLMc4FmDvL0eXTnVzjfZPhDrIe0PlgLddbx6/Dyw9C9HsXMIqLPXC6yTEC4qqMp5JEo8+ZCQliYVrrJsLGV0yqTtxEo3X7I3MfcpGW3P27VcBVeL01WF8Kgva6q8HU1dzi/s3EFUeNsJr5x+zAO2iA7G4xSKlIkz6qhPWRTMd7IB1Cd1hXohTq0KG3msfwVXpGkpswGlJbDHj9rTHd2PUc97DWf2if9DS2eMVRYOTa1I3Pggpolcd/IoQPRJHXNBvYYiyv+rsNZ7TTegH33Mkpc2GavJuI531vQCA+Wec2S8vMI1JTc+q4uLzhZjVgJFJYlZ2Y/O7yYys8i4qdV8tcO1CEhW41vF0QUzCY4oxQG3b41mS6/stTYB+P4Dgg/kYfGThCAp8mg1clz4Zulg128eEahX4ms8q6jVZRfl8HIvnpSuA= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(346002)(376002)(396003)(39860400002)(36840700001)(46966006)(26005)(55016002)(36860700001)(478600001)(186003)(70586007)(16526019)(36756003)(36906005)(8936002)(5660300002)(336012)(426003)(4326008)(6286002)(6666004)(356005)(47076005)(54906003)(82740400003)(70206006)(2616005)(8676002)(316002)(2906002)(7696005)(86362001)(1076003)(7636003)(83380400001)(82310400003)(107886003)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:54.6583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 000d64c9-0a8c-49fc-6744-08d90b25bc22 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5388 Subject: [dpdk-dev] [PATCH v2 10/16] common/mlx5: add crypto BSF struct and defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled This patch adds the struct defining crypto BSF segment of UMR WQE, and the related value definitions and offsets. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index a2437faec0..a9dcbfa63c 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1096,6 +1096,72 @@ struct mlx5_ifc_create_mkey_in_bits { u8 klm_pas_mtt[][0x20]; }; +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, -- 2.25.1