From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A239BA0547; Thu, 29 Apr 2021 17:46:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 935A541328; Thu, 29 Apr 2021 17:45:22 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2087.outbound.protection.outlook.com [40.107.220.87]) by mails.dpdk.org (Postfix) with ESMTP id AF53B4134E for ; Thu, 29 Apr 2021 17:45:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XIhPv70mMHh23qpnNoPabLX4N5O5Br7AhUnv8hUIVZNXEjJ08d9EtPO69Hg5EuJP0bepPhRfrY3OcirCp8GLvBAEnQTw7S4ysHoZzoR7kYriFnenLrj3hk21Mgz3pbqdPJaeuahrS2GrtOH+9iVF9eJcwHwTJKnvGVONT1N9qp5+TVsR3jKIs3frGn8VBs/J3BCVXIfNpZM+sO1DpvCxCG9xZcMk6NNNrsQPclekat5EygeAseklM40yRIBlrENlAT3gnwsMxx5YJ5LARDkkLMI9xG6WNHX5bAYCVRTbVzUzD3Ug+1aobf6pQyXLXg4/3I/yKz5kuycMRCJitYhjHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5+yMpMZHcpWxvo55rWEB6SjMiw3bv9AggldrRGEhyY8=; b=imUeghLDECYNGnd/aZ8hsvcCwXaX2QKM1+5/38BAEg2VOJnKL6hVIdeBMOUUnR2PvUFROcaLkaCgBNK2M8ba8g7fZSOX2pgjGQI88ojPkyPl8QjoQh8s4VSioQ/vpCsrGcyWVme/sjZOyr5TZDMUzwjLN2MwCsUqCD2aeNGpQ4g7GsXBzJnJu7w1XnDpRo5VkEWq/qZKqfj7KY5wvOemNuzf0hBdlv451W0Gu9D+oitMNAYNDlly7KSYMWTMH2Sd77UjuXZ7NbH0t4HRia4s6gcmZa0TPc/onPM//WoxXn3juW7otChfgHWr8AfJT5IWn9ystu2nQukYbfkpr8RK7Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5+yMpMZHcpWxvo55rWEB6SjMiw3bv9AggldrRGEhyY8=; b=TJYQ+ycHQxFuonvMSPATOxHUuO9fALCHVY9tnM+ULjwAB1VSkSz8gTh28CGGOOtv5Y5zUe9eR7zWlkiKMqXBNg7AfqPwRRnSOx8uut0fz9aJFVsOtqCHKK4lr88/G9J8x3twrlvBS6lV9g/WCiCgoBQkcfo7JvI3aeGynSzbvaXhNnC8bsZbCpzxHDjfKuvXMi75Cm6zQaCokCz/h9tuCAkpyQ6iGvavPaOmrPtZVGlsRT7zpudvzTmR9mShR+9EvwhaeZMMbbZ+hX0UsD3/Phohe3UaFuNu6Firfq5wsy5hrgWCNtEN8noR+N0MMDV+SNSgcxwk8yE+R44Z3m4ClA== Received: from DM3PR14CA0129.namprd14.prod.outlook.com (2603:10b6:0:53::13) by BN8PR12MB3586.namprd12.prod.outlook.com (2603:10b6:408:47::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21; Thu, 29 Apr 2021 15:45:08 +0000 Received: from DM6NAM11FT041.eop-nam11.prod.protection.outlook.com (2603:10b6:0:53:cafe::c9) by DM3PR14CA0129.outlook.office365.com (2603:10b6:0:53::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.25 via Frontend Transport; Thu, 29 Apr 2021 15:45:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:45:07 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:05 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:33 +0300 Message-ID: <20210429154335.2820028-15-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-TrafficTypeDiagnostic: BN8PR12MB3586: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DlA+39xu7V/8fi+P7/BGw3ADvCxcQ8CJK3HbbRqAYrtuZXii0V7p3dZz84VitvQ9UTXNjm3n8/YBYngiTrcYfZK6dxow/dilKaM1XAGDOfoYyn9EbpkdfnWN+qwH6+33c4BVnqitTLczC1+hbtPMcDZ/oSZZg3yVAg0cvFg1fhE2CNmycrzrPMgiiAFmRqLf4zdy8rrwB0Y5dBtCyLbVxZ3FHq5pOivK0CNlVjxkS/Qfr3mwKMli2D1maVYpGuCsLCJ1aWNSP8Go8suc3I7i//J+P0Ut4q/h/8VtFwm1UEAv3yNwxDiNBFM6qHrK2/l10DG3ndTOhl7NnJeUdid1X+ynuupsBC8az9NKIezbw7sdTKXzv+MvdWU7Q79xHbmtFZakup5Y5DLNzLNqct2gC9q7C/LxGWwHTP1WXHuiKwDkUsP11wjVCd4TZMcC2fEoAo/09CZloMqgK6Jv0OeKYC9X9SfVo+UfW9/YQlAMucSuu39DGePFGxicAdv0eaVPOA1lxiCu3Dq7nmTbWg2KqBK1FpYwolNL8GY4crhqq8jB1ok5PeBBF2/HzW5y0S2KzElcdb2ncRlMcfhwyvD1Zl/wU8mxlPMWwJyxOAR8XkOeJEFKXm80IsDP/hcDuj4bRuDc7BuVaJWvAMliWUafBst78lEkgPJe8mSVABwfoWo= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(346002)(396003)(39860400002)(136003)(46966006)(36840700001)(82310400003)(8936002)(478600001)(1076003)(336012)(5660300002)(82740400003)(86362001)(2906002)(83380400001)(2616005)(36756003)(426003)(6666004)(36860700001)(55016002)(107886003)(6286002)(7636003)(26005)(36906005)(356005)(186003)(4326008)(54906003)(316002)(6916009)(70586007)(47076005)(8676002)(16526019)(7696005)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:07.9276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3586 Subject: [dpdk-dev] [PATCH v2 14/16] common/mlx5: add crypto register structs and defs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Encryption key management requires use of several related registers. This patch adds the relevant structs and values, according to PRM definitions. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 432c8fdb63..c2cd2d9f70 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3307,6 +3307,10 @@ enum { enum { MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, }; struct mlx5_ifc_register_mtutc_bits { @@ -3324,6 +3328,43 @@ struct mlx5_ifc_register_mtutc_bits { #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + struct mlx5_ifc_parse_graph_arc_bits { u8 start_inner_tunnel[0x1]; u8 reserved_at_1[0x7]; -- 2.25.1