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From: Matan Azrad <matan@nvidia.com>
To: <dev@dpdk.org>
CC: <matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, "Thomas
Monjalon" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>
Date: Tue, 4 May 2021 20:54:58 +0300
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Subject: [dpdk-dev] [PATCH v3 13/15] common/mlx5: add crypto register
structs and defs
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From: Dekel Peled <dekelp@nvidia.com>
Encryption key management requires use of several related registers.
This patch adds the relevant structs and values, according to PRM
definitions.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 41 ++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 432c8fdb63..c2cd2d9f70 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3307,6 +3307,10 @@ enum {
enum {
MLX5_REGISTER_ID_MTUTC = 0x9055,
+ MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
+ MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
+ MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
+ MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
};
struct mlx5_ifc_register_mtutc_bits {
@@ -3324,6 +3328,43 @@ struct mlx5_ifc_register_mtutc_bits {
#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
+struct mlx5_ifc_crypto_operational_register_bits {
+ u8 wrapped_crypto_operational[0x1];
+ u8 reserved_at_1[0x1b];
+ u8 kek_size[0x4];
+ u8 reserved_at_20[0x20];
+ u8 credential[0x140];
+ u8 kek[0x100];
+ u8 reserved_at_280[0x180];
+};
+
+struct mlx5_ifc_crypto_commissioning_register_bits {
+ u8 token[0x1]; /* TODO: add size after PRM update */
+};
+
+struct mlx5_ifc_import_kek_handle_register_bits {
+ struct mlx5_ifc_crypto_login_bits crypto_login_object;
+ struct mlx5_ifc_import_kek_bits import_kek_object;
+ u8 reserved_at_200[0x4];
+ u8 write_operation[0x4];
+ u8 import_kek_id[0x18];
+ u8 reserved_at_220[0xe0];
+};
+
+struct mlx5_ifc_credential_handle_register_bits {
+ struct mlx5_ifc_crypto_login_bits crypto_login_object;
+ struct mlx5_ifc_credential_bits credential_object;
+ u8 reserved_at_200[0x4];
+ u8 write_operation[0x4];
+ u8 credential_id[0x18];
+ u8 reserved_at_220[0xe0];
+};
+
+enum {
+ MLX5_REGISTER_ADD_OPERATION = 0x1,
+ MLX5_REGISTER_DELETE_OPERATION = 0x2,
+};
+
struct mlx5_ifc_parse_graph_arc_bits {
u8 start_inner_tunnel[0x1];
u8 reserved_at_1[0x7];
--
2.25.1