From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D4EFA0524; Thu, 6 May 2021 06:10:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 99595410FE; Thu, 6 May 2021 06:10:22 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id DE1C0410F3 for ; Thu, 6 May 2021 06:10:20 +0200 (CEST) IronPort-SDR: SrHm3pUFa+8Lt+ullg2DbG/4Gj70k02nGz4z9F+doARxbDa0haArHTwuMil38Wig//YIAl/MCD xEIAF2zXRsng== X-IronPort-AV: E=McAfee;i="6200,9189,9975"; a="195251311" X-IronPort-AV: E=Sophos;i="5.82,276,1613462400"; d="scan'208";a="195251311" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2021 21:10:20 -0700 IronPort-SDR: TQ0EbJw8ALwbDmMp50F/b7u4qNgsdmrsm0MmOMNxelFdFd6CHFiUFQReBkgex3RQk22SzXPdYt kUvf1bfz5QsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,276,1613462400"; d="scan'208";a="434147085" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga008.jf.intel.com with ESMTP; 05 May 2021 21:10:18 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, david.marchand@redhat.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Thu, 6 May 2021 11:49:56 +0800 Message-Id: <20210506034957.46458-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210506034957.46458-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210506034957.46458-1-haiyue.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v5 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And if failed, the device or system may be in an invalid state, so keep the VF reset state to mark it as I/O error. Signed-off-by: Haiyue Wang --- drivers/net/iavf/iavf_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index c06873d26..0084a083b 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2356,7 +2356,8 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; - vf->vf_reset = false; + if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true)) + vf->vf_reset = false; return ret; } -- 2.31.1