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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2021 16:05:43.4873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6be406f4-777e-49da-7b8d-08d913044c9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3538 Subject: [dpdk-dev] [PATCH v4 10/14] crypto/mlx5: add maximum segments devarg X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Suanming Mou The mlx5 HW crypto operations are done by attaching crypto property to a memory region. Once done, every access to the memory via the crypto-enabled memory region will result with in-line encryption or decryption of the data. As a result, the design choice is to provide two types of WQEs. One is UMR WQE which sets the crypto property and the other is rdma write WQE which sends DMA command to copy data from local MR to remote MR. The size of the WQEs will be defined by a new devarg called max_segs_num. This devarg also defines the maximum segments in mbuf chain that will be supported for crypto operations. Signed-off-by: Suanming Mou Signed-off-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 35 +++++++++++++++++++++++++++---- drivers/crypto/mlx5/mlx5_crypto.h | 7 +++++++ 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index d4379d2b05..1a7317aef5 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -21,6 +21,7 @@ #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5 #define MLX5_CRYPTO_MAX_QPS 1024 +#define MLX5_CRYPTO_MAX_SEGS 56 TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); @@ -465,14 +466,24 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val); return -errno; } - if (strcmp(key, "import_kek_id") == 0) + if (strcmp(key, "max_segs_num") == 0) { + if (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) { + DRV_LOG(WARNING, "Invalid max_segs_num: %d, should" + " be less than %d.", + (uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS); + rte_errno = EINVAL; + return -rte_errno; + } + devarg_prms->max_segs_num = (uint32_t)tmp; + } else if (strcmp(key, "import_kek_id") == 0) { attr->session_import_kek_ptr = (uint32_t)tmp; - else if (strcmp(key, "credential_id") == 0) + } else if (strcmp(key, "credential_id") == 0) { attr->credential_pointer = (uint32_t)tmp; - else if (strcmp(key, "keytag") == 0) + } else if (strcmp(key, "keytag") == 0) { devarg_prms->keytag = tmp; - else + } else { DRV_LOG(WARNING, "Invalid key %s.", key); + } return 0; } @@ -487,6 +498,7 @@ mlx5_crypto_parse_devargs(struct rte_devargs *devargs, attr->credential_pointer = 0; attr->session_import_kek_ptr = 0; devarg_prms->keytag = 0; + devarg_prms->max_segs_num = 8; if (devargs == NULL) { DRV_LOG(ERR, "No login devargs in order to enable crypto operations in the device."); @@ -627,6 +639,21 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); + priv->max_segs_num = devarg_prms.max_segs_num; + priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + + sizeof(struct mlx5_umr_wqe) + + RTE_ALIGN(priv->max_segs_num, 4) * + sizeof(struct mlx5_wqe_dseg); + priv->rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + + sizeof(struct mlx5_wqe_dseg) * + (priv->max_segs_num <= 2 ? 2 : 2 + + RTE_ALIGN(priv->max_segs_num - 2, 4)); + priv->wqe_set_size = priv->umr_wqe_size + priv->rdmw_wqe_size; + priv->wqe_stride = (priv->umr_wqe_size + priv->rdmw_wqe_size) / + MLX5_SEND_WQE_BB; + priv->max_rdmaw_klm_n = (priv->rdmw_wqe_size - + sizeof(struct mlx5_rdma_write_wqe)) / + sizeof(struct mlx5_wqe_dseg); pthread_mutex_lock(&priv_list_lock); TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next); pthread_mutex_unlock(&priv_list_lock); diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 34c65f9a24..81452bd700 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -25,12 +25,18 @@ struct mlx5_crypto_priv { struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ uint32_t pdn; /* Protection Domain number. */ + uint32_t max_segs_num; /* Maximum supported data segs. */ struct ibv_pd *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ struct mlx5_devx_obj *login_obj; uint64_t keytag; + uint16_t wqe_set_size; + uint16_t umr_wqe_size; + uint16_t rdmw_wqe_size; + uint16_t wqe_stride; + uint16_t max_rdmaw_klm_n; }; struct mlx5_crypto_qp { @@ -54,6 +60,7 @@ struct mlx5_crypto_devarg_params { bool login_devarg; struct mlx5_devx_crypto_login_attr login_attr; uint64_t keytag; + uint32_t max_segs_num; }; int -- 2.25.1