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Wed, 19 May 2021 13:33:19 -0400 (EDT)
From: Thomas Monjalon <thomas@monjalon.net>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, asafp@nvidia.com,
Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,
Ajit Khaparde <ajit.khaparde@broadcom.com>, Ori Kam <orika@nvidia.com>
Date: Wed, 19 May 2021 19:33:16 +0200
Message-Id: <20210519173316.2364189-1-thomas@monjalon.net>
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Subject: [dpdk-dev] [PATCH v2] ethdev: fix comments of packet integrity flow
item
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The Doxygen comments are placed before the related lines,
but the markers were /**< instead of /**
The struct rte_flow_item_integrity did not appear in Doxygen output
because there was no general comment for the struct.
Fixes: b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
v2: add general comment for the struct (thanks Ferruh for the catch)
---
lib/ethdev/rte_flow.h | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index 94c8c1ccc8..961a5884fe 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -1707,8 +1707,16 @@ rte_flow_item_geneve_opt_mask = {
};
#endif
+/**
+ * @warning
+ * @b EXPERIMENTAL: this structure may change without prior notice
+ *
+ * RTE_FLOW_ITEM_TYPE_INTEGRITY
+ *
+ * Match on packet integrity check result.
+ */
struct rte_flow_item_integrity {
- /**< Tunnel encapsulation level the item should apply to.
+ /** Tunnel encapsulation level the item should apply to.
* @see rte_flow_action_rss
*/
uint32_t level;
@@ -1716,21 +1724,21 @@ struct rte_flow_item_integrity {
union {
__extension__
struct {
- /**< The packet is valid after passing all HW checks. */
+ /** The packet is valid after passing all HW checks. */
uint64_t packet_ok:1;
- /**< L2 layer is valid after passing all HW checks. */
+ /** L2 layer is valid after passing all HW checks. */
uint64_t l2_ok:1;
- /**< L3 layer is valid after passing all HW checks. */
+ /** L3 layer is valid after passing all HW checks. */
uint64_t l3_ok:1;
- /**< L4 layer is valid after passing all HW checks. */
+ /** L4 layer is valid after passing all HW checks. */
uint64_t l4_ok:1;
- /**< L2 layer CRC is valid. */
+ /** L2 layer CRC is valid. */
uint64_t l2_crc_ok:1;
- /**< IPv4 layer checksum is valid. */
+ /** IPv4 layer checksum is valid. */
uint64_t ipv4_csum_ok:1;
- /**< L4 layer checksum is valid. */
+ /** L4 layer checksum is valid. */
uint64_t l4_csum_ok:1;
- /**< The l3 length is smaller than the frame length. */
+ /** L3 length is smaller than frame length. */
uint64_t l3_len_ok:1;
uint64_t reserved:56;
};
--
2.31.1