From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5A33EA0547; Mon, 24 May 2021 03:44:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 41F0C41109; Mon, 24 May 2021 03:44:42 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 6725A41108 for ; Mon, 24 May 2021 03:44:40 +0200 (CEST) IronPort-SDR: Dsx/MSKr7qwfiAr5Xhf6WgyZS2+rbR7I5clsLhRs72NrXwggSpy0M70yBCWAkl/P9QhZunGdWU jzvrPoA12DuQ== X-IronPort-AV: E=McAfee;i="6200,9189,9993"; a="201573599" X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="201573599" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2021 18:44:38 -0700 IronPort-SDR: H+u+8QBDvOyXdOt9k/n9J3nof18J+qxlUkGFaFCuT7GOHVmhz8mLCsv2veHjHU8w+zH+bHlsTp xsftFIbcO4YA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="441824235" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga008.jf.intel.com with ESMTP; 23 May 2021 18:44:36 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, david.marchand@redhat.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Mon, 24 May 2021 09:23:44 +0800 Message-Id: <20210524012346.496560-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210524012346.496560-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210524012346.496560-1-haiyue.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggered by the PF reset event, then the PCI bus master will be cleared, the VF will be not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And if failed, the device or system may be in an invalid state, so keep the VF reset state to mark it as I/O error. Signed-off-by: Haiyue Wang --- drivers/net/iavf/iavf_ethdev.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d688c31cfb..a7ef7a6d4d 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2356,7 +2356,15 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; - vf->vf_reset = false; + /* + * If the VF is reset via VFLR, the device will be knocked out of bus + * master mode, and the driver will fail to recover from the reset. Fix + * this by enabling bus mastering after every reset. In a non-VFLR case, + * the bus master bit will not be disabled, and this call will have no + * effect. + */ + if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true)) + vf->vf_reset = false; return ret; } -- 2.31.1