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From: Muhammad Ahmad <muhammad.ahmad@emumba.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, qi.z.zhang@intel.com,
	bruce.richardson@intel.com, konstantin.ananyev@intel.com,
	jia.guo@intel.com, beilei.xing@intel.com,
	Muhammad Ahmad <muhammad.ahmad@emumba.com>
Subject: [dpdk-dev] [RFC] Add selection between vector and scalar mode in ixgbe
Date: Tue, 25 May 2021 11:58:18 +0500	[thread overview]
Message-ID: <20210525065818.10379-1-muhammad.ahmad@emumba.com> (raw)


The selection between scalar mode and vector mode was removed for
ixgbe driver in DPDK 20.02. The code base still has code
for scalar mode but it cannot be selected at compile time. The
vector mode is adequate for applications which require high
throughput which is the case most of the time, but scalar mode has
a use case in ultra-low-latency fintech applications for algorithmic
trading. This use case was also presented at the DPDK userspace
summit in September 2020.
This patch enables the ability to select between scalar and vector
modes for ixgbe drivers in the config.
In the future we can introduce API in ehtdev, which allow user to
select between latency and throughput mode.  

Signed-off-by: Muhammad Ahmad <muhammad.ahmad@emumba.com>
---
 config/rte_config.h              | 3 +++
 drivers/net/ixgbe/ixgbe_ethdev.c | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/config/rte_config.h b/config/rte_config.h
index 8aa46a1aa..cc30f7f39 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -121,6 +121,9 @@
 /* hns3 defines */
 #define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256
 
+/*ixgbe defines*/
+#define RTE_IXGBE_SCALAR_ENABLE 0
+
 /* i40e defines */
 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 00101c2ee..c992dc7e5 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -84,7 +84,7 @@
 #define IXGBE_DEFAULT_RX_WTHRESH      0
 
 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 #define IXGBE_DEFAULT_TX_PTHRESH      32
 #define IXGBE_DEFAULT_TX_HTHRESH      0
 #define IXGBE_DEFAULT_TX_WTHRESH      0
 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
@@ -2415,6 +2415,12 @@ ixgbe_dev_configure(struct rte_eth_dev *dev)
 	 */
 	adapter->rx_bulk_alloc_allowed = true;
 	adapter->rx_vec_allowed = true;
+
+	#if RTE_IXGBE_SCALAR_ENABLE == 1
+	adapter->rx_vec_allowed = false;
+	#endif
 
 	return 0;
 }
@@ -9121,3 +9127,4 @@ RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
 #endif
+
-- 
2.17.1


             reply	other threads:[~2021-05-25  6:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25  6:58 Muhammad Ahmad [this message]
2021-05-25  9:22 ` Bruce Richardson

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