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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT017.mail.protection.outlook.com (10.13.175.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4150.30 via Frontend Transport; Mon, 31 May 2021 10:21:13 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 10:20:14 +0000 From: rongwei liu To: , , , CC: , Date: Mon, 31 May 2021 13:19:39 +0300 Message-ID: <20210531101941.60916-1-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c60cf1f-8102-413c-7c75-08d9241dd1a8 X-MS-TrafficTypeDiagnostic: MWHPR12MB1487: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 10:21:13.8518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c60cf1f-8102-413c-7c75-08d9241dd1a8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1487 Subject: [dpdk-dev] [RFC 0/2] support VXLAN header last 8-bits matching X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This update adds support for the VXLAN last 8-bits matching when creating steering rules. At the PCIe probe stage, we create a dummy VXLAN matcher using misc5 to check rdma-core library's capability. The logic is, group 0 depends on HCA_CAP to enable misc or misc5 for VXLAN matching while group non zero depends on the rdma-core capability. Add a new testpmd pattern field 'last_rsvd' that supports the last 8-bits matching of VXLAN header. The examples for the "last_rsvd" pattern field are as below: 1. ...pattern eth / ipv4 / udp / vxlan last_rsvd is 0x80 / end ... This flow will exactly match the last 8-bits to be 0x80. 2. ...pattern eth / ipv4 / udp / vxlan last_rsvd spec 0x80 vxlan mask 0x80 / end ... This flow will only match the MSB of the last 8-bits to be 1. rongwei liu (2): drivers: add VXLAN header the last 8-bits matching support app/testpmd: support VXLAN last 8-bits field matching app/test-pmd/cmdline_flow.c | 9 ++ app/test-pmd/util.c | 5 +- doc/guides/nics/mlx5.rst | 11 +- doc/guides/testpmd_app_ug/testpmd_funcs.rst | 1 + drivers/common/mlx5/mlx5_devx_cmds.c | 3 + drivers/common/mlx5/mlx5_devx_cmds.h | 6 + drivers/common/mlx5/mlx5_prm.h | 41 +++++- drivers/net/mlx5/linux/mlx5_os.c | 77 ++++++++++ drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_flow.c | 26 +++- drivers/net/mlx5/mlx5_flow.h | 4 +- drivers/net/mlx5/mlx5_flow_dv.c | 152 ++++++++++++++------ drivers/net/mlx5/mlx5_flow_verbs.c | 3 +- drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 6 +- 14 files changed, 283 insertions(+), 63 deletions(-) -- 2.27.0